device,sb/intel: Move SMBus host controller prototypes
Also change some of the types to match the register widths of the controller. It is expected that these prototypes will be used with SMBus host controllers inside AMD chipsets as well, thus the change of location. Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
parent
5e9ae0c2bc
commit
1cae45432e
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@ -0,0 +1,35 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DEVICE_SMBUS_HOST_H__
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#define __DEVICE_SMBUS_HOST_H__
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#include <stdint.h>
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/* Low-level SMBUS host controller. */
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int do_smbus_recv_byte(uintptr_t base, u8 device);
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int do_smbus_send_byte(uintptr_t base, u8 device, u8 val);
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int do_smbus_read_byte(uintptr_t base, u8 device, u8 address);
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int do_smbus_write_byte(uintptr_t base, u8 device, u8 address, u8 data);
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int do_smbus_read_word(uintptr_t base, u8 device, u8 address);
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int do_smbus_write_word(uintptr_t base, u8 device, u8 address, u16 data);
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int do_smbus_block_read(uintptr_t base, u8 device, u8 cmd, size_t max_bytes, u8 *buf);
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int do_smbus_block_write(uintptr_t base, u8 device, u8 cmd, size_t bytes, const u8 *buf);
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/* For Intel, implemented since ICH5. */
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int do_i2c_eeprom_read(uintptr_t base, u8 device, u8 offset, size_t bytes, u8 *buf);
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int do_i2c_block_write(uintptr_t base, u8 device, size_t bytes, u8 *buf);
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#endif
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@ -23,11 +23,11 @@
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#include <arch/cpu.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <device/smbus_host.h>
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#include <cbmem.h>
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#include <timestamp.h>
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#include <mrc_cache.h>
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#include <southbridge/intel/bd82x6x/me.h>
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#include <southbridge/intel/common/smbus.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <cpu/x86/msr.h>
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#include <types.h>
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@ -20,8 +20,8 @@
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#include <device/pci_def.h>
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#include <device/pci_type.h>
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#include <device/pci_ops.h>
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#include <device/smbus_host.h>
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#include <soc/smbus.h>
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#include <southbridge/intel/common/smbus.h>
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int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
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{
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@ -25,6 +25,7 @@
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#include <soc/ramstage.h>
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#include <soc/smbus.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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static void pch_smbus_init(struct device *dev)
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{
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@ -21,6 +21,7 @@
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#include <device/pci_ids.h>
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#include <soc/smbus.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "smbuslib.h"
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static int lsmbus_read_byte(struct device *dev, u8 address)
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@ -15,7 +15,7 @@
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#include <console/console.h>
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#include <spd_bin.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include <string.h>
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#include "smbuslib.h"
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@ -19,6 +19,7 @@
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "pch.h"
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void enable_smbus(void)
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@ -22,6 +22,7 @@
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "pch.h"
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static void pch_smbus_init(struct device *dev)
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@ -19,6 +19,7 @@
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/smbus_def.h>
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#include <device/smbus_host.h>
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#include <types.h>
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#include "smbus.h"
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@ -332,30 +333,27 @@ static int block_cmd_loop(uintptr_t base, u8 *buf, size_t max_bytes, int flags)
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return bytes;
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}
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int do_smbus_read_byte(unsigned int smbus_base, u8 device, unsigned int address)
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int do_smbus_read_byte(uintptr_t smbus_base, u8 device, u8 address)
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{
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return smbus_read_cmd(smbus_base, I801_BYTE_DATA, device, address);
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}
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int do_smbus_read_word(unsigned int smbus_base, u8 device, unsigned int address)
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int do_smbus_read_word(uintptr_t smbus_base, u8 device, u8 address)
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{
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return smbus_read_cmd(smbus_base, I801_WORD_DATA, device, address);
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}
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int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address,
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unsigned int data)
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int do_smbus_write_byte(uintptr_t smbus_base, u8 device, u8 address, u8 data)
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{
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return smbus_write_cmd(smbus_base, I801_BYTE_DATA, device, address, data);
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}
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int do_smbus_write_word(unsigned int smbus_base, u8 device, unsigned int address,
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unsigned int data)
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int do_smbus_write_word(uintptr_t smbus_base, u8 device, u8 address, u16 data)
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{
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return smbus_write_cmd(smbus_base, I801_WORD_DATA, device, address, data);
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}
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int do_smbus_block_read(unsigned int smbus_base, u8 device, u8 cmd,
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unsigned int max_bytes, u8 *buf)
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int do_smbus_block_read(uintptr_t smbus_base, u8 device, u8 cmd, size_t max_bytes, u8 *buf)
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{
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int ret, slave_bytes;
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@ -382,8 +380,7 @@ int do_smbus_block_read(unsigned int smbus_base, u8 device, u8 cmd,
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return ret;
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}
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int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd,
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const unsigned int bytes, const u8 *buf)
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int do_smbus_block_write(uintptr_t smbus_base, u8 device, u8 cmd, const size_t bytes, const u8 *buf)
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{
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int ret;
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@ -418,8 +415,7 @@ static int has_i2c_read_command(void)
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return 1;
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}
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int do_i2c_eeprom_read(unsigned int smbus_base, u8 device,
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unsigned int offset, const unsigned int bytes, u8 *buf)
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int do_i2c_eeprom_read(uintptr_t smbus_base, u8 device, u8 offset, const size_t bytes, u8 *buf)
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{
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int ret;
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@ -456,8 +452,7 @@ int do_i2c_eeprom_read(unsigned int smbus_base, u8 device,
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* The caller is responsible of settings HOSTC I2C_EN bit prior to making this
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* call!
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*/
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int do_i2c_block_write(unsigned int smbus_base, u8 device,
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unsigned int bytes, u8 *buf)
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int do_i2c_block_write(uintptr_t smbus_base, u8 device, size_t bytes, u8 *buf)
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{
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u8 cmd;
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int ret;
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@ -32,22 +32,4 @@
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#define SMBUS_PIN_CTL 0xf
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#define SMBSLVCMD 0x11
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int do_smbus_read_byte(unsigned int smbus_base, u8 device,
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unsigned int address);
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int do_smbus_write_byte(unsigned int smbus_base, u8 device,
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unsigned int address, unsigned int data);
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int do_smbus_read_word(unsigned int smbus_base, u8 device,
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unsigned int address);
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int do_smbus_write_word(unsigned int smbus_base, u8 device,
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unsigned int address, unsigned int data);
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int do_smbus_block_read(unsigned int smbus_base, u8 device,
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u8 cmd, unsigned int max_bytes, u8 *buf);
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int do_smbus_block_write(unsigned int smbus_base, u8 device,
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u8 cmd, unsigned int bytes, const u8 *buf);
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/* Only since ICH5 */
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int do_i2c_eeprom_read(unsigned int smbus_base, u8 device,
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unsigned int offset, unsigned int bytes, u8 *buf);
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int do_i2c_block_write(unsigned int smbus_base, u8 device,
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unsigned int bytes, u8 *buf);
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#endif
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@ -21,6 +21,7 @@
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "i82371eb.h"
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void enable_smbus(void)
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@ -25,7 +25,6 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/smbus.h>
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#include <southbridge/intel/common/smbus.h>
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#include "chip.h"
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#include "i82371eb.h"
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "i82801dx.h"
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@ -19,6 +19,7 @@
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "i82801gx.h"
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void enable_smbus(void)
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@ -19,7 +19,7 @@
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#include <device/smbus.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "i82801gx.h"
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static int lsmbus_read_byte(struct device *dev, u8 address)
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "i82801ix.h"
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void enable_smbus(void)
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@ -20,7 +20,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "i82801ix.h"
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static void pch_smbus_init(struct device *dev)
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@ -20,6 +20,7 @@
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "i82801jx.h"
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void enable_smbus(void)
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@ -20,7 +20,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "i82801jx.h"
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static void pch_smbus_init(struct device *dev)
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@ -19,6 +19,7 @@
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "pch.h"
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void enable_smbus(void)
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@ -22,6 +22,7 @@
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "pch.h"
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static void pch_smbus_init(struct device *dev)
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "pch.h"
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void enable_smbus(void)
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <southbridge/intel/common/smbus.h>
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#include <device/smbus_host.h>
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#include "pch.h"
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static void pch_smbus_init(struct device *dev)
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