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soc/amd/mendocino: Add low/no battery VRM limit registers 

Add DPTC Low/No battery VRM limit registers to throttle the SOC.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Van Patten 2022-09-15 17:15:56 -06:00 committed by Martin L Roth
parent 11ca995500
commit 1cf0acdc1c
1 changed files with 4 additions and 0 deletions
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4
src/soc/amd/mendocino/chip.h
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@ -68,6 +68,10 @@ struct soc_amd_mendocino_config {
uint32_t vrm_current_limit_mA;
uint32_t vrm_maximum_current_limit_mA;
uint32_t vrm_soc_current_limit_mA;
/* Throttle (e.g., Low/No Battery) */
uint32_t vrm_current_limit_throttle_mA;
uint32_t vrm_maximum_current_limit_throttle_mA;
uint32_t vrm_soc_current_limit_throttle_mA;
uint8_t smartshift_enable;