We are adding this obsolete, deprecated part to support the momentum
apache board. We're not filling in all the support, since it appears nobody uses this part. If you really need parallel port support, add it. We hope to remove this part in future if the only board using it moves to a newer part. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
20d943d9f9
commit
1cf26a8884
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config chip.h
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object superio.o
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#ifndef SIO_COM1
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#define SIO_COM1_BASE 0x3F8
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#endif
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#ifndef SIO_COM2
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#define SIO_COM2_BASE 0x2F8
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#endif
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extern struct chip_operations superio_NSC_pc87417_ops;
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#include <pc80/keyboard.h>
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#include <uart8250.h>
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struct superio_NSC_pc87417_config {
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struct uart8250 com1, com2;
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struct pc_keyboard keyboard;
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};
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#define PC87417_FDC 0x00 /* Floppy */
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#define PC87417_PP 0x01 /* Parallel Port */
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#define PC87417_SP2 0x02 /* Com2 */
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#define PC87417_SP1 0x03 /* Com1 */
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#define PC87417_SWC 0x04 /* System Wake-Up Controller (SWC) */
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#define PC87417_KBCM 0x05 /* Mouse */
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#define PC87417_KBCK 0x06 /* Keyboard */
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#define PC87417_GPIO 0x07
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#define PC87417_XBUS 0x0F
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#define PC87417_RTC 0x10
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#define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO)
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/* This is to get around a romcc bug */
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//#define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS)
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#define PC87417_XBUS_DEV PNP_DEV(0x2e, 0x0f)
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#define PC87417_GPSEL 0xf0
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#define PC87417_GPCFG1 0xf1
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#define PC87417_GPEVR 0xf2
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#define PC87417_GPCFG2 0xf3
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#define PC87417_EXTCFG 0xf4
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#define PC87417_IOEXT1A 0xf5
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#define PC87417_IOEXT1B 0xf6
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#define PC87417_IOEXT2A 0xf7
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#define PC87417_IOEXT2B 0xf8
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#define PC87417_GPDO_0 0x00
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#define PC87417_GPDI_0 0x01
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#define PC87417_GPDO_1 0x02
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#define PC87417_GPDI_1 0x03
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#define PC87417_GPEVEN_1 0x04
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#define PC87417_GPEVST_1 0x05
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#define PC87417_GPDO_2 0x06
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#define PC87417_GPDI_2 0x07
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#define PC87417_GPDO_3 0x08
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#define PC87417_GPDI_3 0x09
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#define PC87417_GPDO_4 0x0a
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#define PC87417_GPDI_4 0x0b
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#define PC87417_GPEVEN_4 0x0c
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#define PC87417_GPEVST_4 0x0d
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#define PC87417_GPDO_5 0x0e
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#define PC87417_GPDI_5 0x0f
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#define PC87417_GPDO_6 0x10
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#define PC87417_GPDO_7A 0x11
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#define PC87417_GPDO_7B 0x12
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#define PC87417_GPDO_7C 0x13
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#define PC87417_GPDO_7D 0x14
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#define PC87417_GPDI_7A 0x15
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#define PC87417_GPDI_7B 0x16
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#define PC87417_GPDI_7C 0x17
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#define PC87417_GPDI_7D 0x18
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#define PC87417_XIOCNF 0xf0
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#define PC87417_XIOBA1H 0xf1
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#define PC87417_XIOBA1L 0xf2
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#define PC87417_XIOSIZE1 0xf3
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#define PC87417_XIOBA2H 0xf4
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#define PC87417_XIOBA2L 0xf5
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#define PC87417_XIOSIZE2 0xf6
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#define PC87417_XMEMCNF1 0xf7
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#define PC87417_XMEMCNF2 0xf8
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#define PC87417_XMEMBAH 0xf9
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#define PC87417_XMEMBAL 0xfa
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#define PC87417_XMEMSIZE 0xfb
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#define PC87417_XIRQMAP1 0xfc
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#define PC87417_XIRQMAP2 0xfd
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#define PC87417_XBIMM 0xfe
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#define PC87417_XBBSL 0xff
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#define PC87417_XBCNF 0x00
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#define PC87417_XZCNF0 0x01
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#define PC87417_XZCNF1 0x02
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#define PC87417_XIRQC0 0x04
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#define PC87417_XIRQC1 0x05
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#define PC87417_XIRQC2 0x06
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#define PC87417_XIMA0 0x08
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#define PC87417_XIMA1 0x09
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#define PC87417_XIMA2 0x0a
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#define PC87417_XIMA3 0x0b
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#define PC87417_XIMD 0x0c
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#define PC87417_XZCNF2 0x0d
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#define PC87417_XZCNF3 0x0e
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#define PC87417_XZM0 0x0f
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#define PC87417_XZM1 0x10
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#define PC87417_XZM2 0x11
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#define PC87417_XZM3 0x12
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#define PC87417_HAP0 0x13
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#define PC87417_HAP1 0x14
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#define PC87417_XSCNF 0x15
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#define PC87417_XWBCNF 0x16
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#include <arch/romcc_io.h>
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#include "pc87417.h"
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static void pc87417_disable_dev(device_t dev)
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{
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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}
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static void pc87417_enable_dev(device_t dev, unsigned iobase)
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{
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_enable(dev, 1);
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}
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static void xbus_cfg(device_t dev)
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{
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uint8_t i, data;
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uint16_t xbus_index;
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pnp_set_logical_device(dev);
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/* select proper BIOS size (4MB) */
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pnp_write_config(dev, PC87417_XMEMCNF2, (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
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xbus_index = pnp_read_iobase(dev, 0x60);
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/* enable writes to devices attached to XCS0 (XBUS Chip Select 0) */
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for (i=0; i<= 0xf; i++) {
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outb((i<<4), xbus_index + PC87417_HAP0);
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}
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return;
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}
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/* Copyright 2000 AG Electronics Ltd. */
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/* Copyright 2003-2004 Linux Networx */
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/* This code is distributed without warranty under the GPL v2 (see COPYING) */
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <console/console.h>
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#include <string.h>
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#include <bitops.h>
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#include "chip.h"
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#include "pc87417.h"
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static void init(device_t dev)
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{
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struct superio_NSC_pc87417_config *conf;
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struct resource *res0, *res1;
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/* Wishlist handle well known programming interfaces more
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* generically.
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*/
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if (!dev->enabled) {
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return;
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}
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conf = dev->chip_info;
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switch(dev->path.u.pnp.device) {
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case PC87417_SP1:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com1);
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break;
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case PC87417_SP2:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com2);
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break;
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case PC87417_KBCK:
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res0 = find_resource(dev, PNP_IDX_IO0);
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res1 = find_resource(dev, PNP_IDX_IO1);
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init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
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break;
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}
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_enable,
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.init = init,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
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{ &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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{ &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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{ &ops, PC87417_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0,
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{ 0xfff0, 0 }, { 0xfffc, 0 }, { 0xfffc, 0 }, { 0xfff8, 0 } },
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{ &ops, PC87417_KBCM, PNP_IRQ0 },
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{ &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
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{ &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
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{ &ops, PC87417_WDT, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
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{ &ops, PC87417_FMC, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
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{ &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
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{ &ops, PC87417_RTC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xfffe, 0 }, { 0xfffe, 0 } },
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{ &ops, PC87417_MHC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffe0, 0 }, { 0xffe0, 0 } },
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops,
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sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
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}
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struct chip_operations superio_NSC_pc87417_ops = {
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CHIP_NAME("NSC 87417")
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.enable_dev = enable_dev,
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};
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