intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() call

Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-01-07 12:00:31 +02:00 committed by Patrick Georgi
parent 7adc370dc7
commit 1cfafe25e3
5 changed files with 7 additions and 6 deletions

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@ -1723,9 +1723,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}
}
/* Enable SMBUS. */
enable_smbus();
/* Collect information about DIMMs and find common settings. */
collect_dimm_config(sysinfo);

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@ -34,8 +34,6 @@ void mainboard_romstage_entry(void)
u8 boot_path = 0;
u8 s3_resume;
enable_smbus();
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
i82801jx_early_init();
#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)

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@ -23,6 +23,9 @@ void i82801ix_early_init(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
if (ENV_ROMSTAGE)
enable_smbus();
/* Set up RCBA. */
pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);

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@ -81,6 +81,9 @@ void i82801jx_early_init(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
if (ENV_ROMSTAGE)
enable_smbus();
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
i82801jx_setup_bars();
printk(BIOS_DEBUG, " done.\n");

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@ -225,8 +225,8 @@ static inline int lpc_is_mobile(const u16 devid)
}
#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
#if ENV_ROMSTAGE
void enable_smbus(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);
int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
u8 *buf);