intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() call
Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1723,9 +1723,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
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while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}
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}
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/* Enable SMBUS. */
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enable_smbus();
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/* Collect information about DIMMs and find common settings. */
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collect_dimm_config(sysinfo);
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@ -34,8 +34,6 @@ void mainboard_romstage_entry(void)
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u8 boot_path = 0;
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u8 s3_resume;
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enable_smbus();
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#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
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i82801jx_early_init();
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#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
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@ -23,6 +23,9 @@ void i82801ix_early_init(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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if (ENV_ROMSTAGE)
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enable_smbus();
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/* Set up RCBA. */
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pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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@ -81,6 +81,9 @@ void i82801jx_early_init(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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if (ENV_ROMSTAGE)
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enable_smbus();
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printk(BIOS_DEBUG, "Setting up static southbridge registers...");
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i82801jx_setup_bars();
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printk(BIOS_DEBUG, " done.\n");
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@ -225,8 +225,8 @@ static inline int lpc_is_mobile(const u16 devid)
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}
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#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
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#if ENV_ROMSTAGE
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void enable_smbus(void);
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#if ENV_ROMSTAGE
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int smbus_read_byte(unsigned int device, unsigned int address);
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int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
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u8 *buf);
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