intel/kunimitsu FAB3: Configure LPC to Quiet Mode.

This patch configures the LPC to quiet mode and sets
enables CLKRUN so that LPC can be power gated.

BUG=chrome-os-partner:44993
BRANCH=none
TEST=Builds and Boots on fab3 kunimitsu.

Change-Id: I46ff21f75b70f54da3f12dcc56d61f84b436cd7d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: edd37df385bc013b62f26435267291acc0a9b9a4
Original-Change-Id: Ide0f9e91127aebb8ac027ee0a598608b50aa4278
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/305396
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/12153
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
pchandri 2015-09-09 17:22:09 -07:00 committed by Patrick Georgi
parent f16bb7cce3
commit 1d77c721d3
3 changed files with 5 additions and 1 deletions

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@ -119,7 +119,7 @@ config SERIAL_CPU_INIT
config SERIRQ_CONTINUOUS_MODE config SERIRQ_CONTINUOUS_MODE
bool bool
default y default n
help help
If you set this option to y, the serial IRQ machine will be If you set this option to y, the serial IRQ machine will be
operated in continuous mode. operated in continuous mode.

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@ -54,4 +54,6 @@
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LGMR 0x98 /* LPC Generic Memory Range */ #define LGMR 0x98 /* LPC Generic Memory Range */
#define BIOS_CNTL 0xdc #define BIOS_CNTL 0xdc
#define PCCTL 0xE0 /* PCI Clock Control */
#define CLKRUN_EN (1 << 0)
#endif #endif

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@ -153,6 +153,8 @@ static const struct reg_script pch_misc_init_script[] = {
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) #if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
#endif #endif
/* Enable CLKRUN_EN for power gating LPC */
REG_PCI_OR8(PCCTL, (CLKRUN_EN)),
REG_SCRIPT_END REG_SCRIPT_END
}; };