soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
On systems that use the first 128kByte of the SPI flash for the EC firmware, it is not possible to place the EFS/amdfw part at the lowest location in flash where the on-chip PSP firmware will look for the EFS, since this is at an offset of 128kByte into the flash which is where the cbfs master header resides when the main CBFS is placed right after the EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION option that allows putting the EFS in a separate FMAP section that can be located right after the EC firmware FMAP section. The EFS FMAP partition is checked to ensure it begins at the expected location. Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -27,3 +27,11 @@ config SOC_AMD_PSP_SELECTABLE_SMU_FW
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and each mainboard can choose to select an appropriate fanless or
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fanned set of blobs. Ask your AMD representative whether your APU
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is considered fanless.
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config AMD_SOC_SEPARATE_EFS_SECTION
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bool
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help
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Use separate EFS FMAP section instead of putting EFS into CBFS. The
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FMAP section must begin exactly at the location the EFS needs to be
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placed in the flash. This option can be used to place the EFS right
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after the 128kByte EC firmware at the beginning of the flash.
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@ -6,6 +6,7 @@ smm-y += psp.c
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smm-y += psp_smm.c
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bootblock-y += psp_efs.c
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bootblock-$(CONFIG_AMD_SOC_SEPARATE_EFS_SECTION) += efs_fmap_check.c
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verstage-y += psp_efs.c
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endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/psp_efs.h>
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#include <assert.h>
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#include <fmap_config.h>
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#include <soc/iomap.h>
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_Static_assert(FMAP_SECTION_EFS_START == (FLASH_BASE_ADDR + EFS_OFFSET),
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"FMAP EFS Offset does not match EFS Offset - check your config");
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