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soc/intel/cannonlake: Align SATA mode names with soc/skl 

Align the SATA mode names with soc/skl providing a consistent API.

Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer 2020-12-07 01:28:59 +01:00 committed by Michael Niewöhner
parent 77562cf95e
commit 1e3b2ce061
7 changed files with 8 additions and 8 deletions
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2
src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
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@ -113,7 +113,7 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "SataMode" = "Sata_AHCI"
register "SataMode" = "SATA_AHCI"
register "SataSalpSupport" = "1"
# Port 2 (J_SSD2)
register "SataPortsEnable[1]" = "1"

2
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -20,7 +20,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SkipExtGfxScan" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
# Configure devslp pad reset to PLT_RST

2
src/mainboard/google/sarien/variants/arcada/devicetree.cb
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@ -16,7 +16,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
register "SkipExtGfxScan" = "1"

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
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@ -16,7 +16,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"

2
src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
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@ -172,7 +172,7 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "SataMode" = "Sata_AHCI"
register "SataMode" = "SATA_AHCI"
register "SataPortsEnable[0]" = "1" # 2.5"
register "SataPortsEnable[2]" = "1" # m.2
register "satapwroptimize" = "1"

2
src/mainboard/system76/lemp9/devicetree.cb
View File

@ -113,7 +113,7 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "SataMode" = "Sata_AHCI"
register "SataMode" = "SATA_AHCI"
register "SataSalpSupport" = "1"
# Port 2 (J_SSD2)
register "SataPortsEnable[1]" = "1"

4
src/soc/intel/cannonlake/chip.h
View File

@ -129,8 +129,8 @@ struct soc_intel_cannonlake_config {
/* SATA related */
enum {
Sata_AHCI,
Sata_RAID,
SATA_AHCI,
SATA_RAID,
} SataMode;
/* SATA devslp pad reset configuration */