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soc/intel/meteorlake/romstage: Rewrite the if condition 

The patch rewrites `if` condition by connecting two different conditions
using the logical and(&&) operator without changing the semantics to
improve the code readability.

TEST=Build the code for Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
This commit is contained in:
Sridhar Siricilla 2022-12-08 11:40:02 +05:30
parent 1542d16173
commit 1e638ba27c
1 changed files with 4 additions and 6 deletions
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10
src/soc/intel/meteorlake/romstage/romstage.c
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@ -130,12 +130,10 @@ void mainboard_romstage_entry(void)
cse_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
if (!s3wake) {
if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
timestamp_add_now(TS_CSE_FW_SYNC_END);
}
if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
timestamp_add_now(TS_CSE_FW_SYNC_END);
}
/*