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soc/intel/adl: Add config option to enable FSP-S SATA test mode 

For further info on SATA test mode, please refer to this doc:
https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/sata-mqst-setup-paper.pdf

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I6ef79fc5723348d5fd10b2ac0847191fa4f37f41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lean Sheng Tan 2022-09-07 16:07:33 +02:00 committed by Felix Held
parent 7c3e48c573
commit 1ec8f97782
2 changed files with 8 additions and 0 deletions
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6
src/soc/intel/alderlake/Kconfig
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@ -317,6 +317,12 @@ config SOC_INTEL_ALDERLAKE_S3
help help
Select if using S3 instead of S0ix to disable D3Cold. Select if using S3 instead of S0ix to disable D3Cold.
config ENABLE_SATA_TEST_MODE
bool "Enable test mode for SATA margining"
default n
help
Enable SATA test mode in FSP-S.
config SOC_INTEL_UART_DEV_MAX config SOC_INTEL_UART_DEV_MAX
int int
default 7 default 7

2
src/soc/intel/alderlake/fsp_params.c
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@ -757,6 +757,8 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
* these disable variables to 1 in devicetree overrides. * these disable variables to 1 in devicetree overrides.
*/ */
s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable); s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable);
/* Test mode for SATA margining */
s_cfg->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE);
/* /*
* Enable DEVSLP Idle Timeout settings DmVal and DitoVal. * Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
* SataPortsDmVal is the DITO multiplier. Default is 15. * SataPortsDmVal is the DITO multiplier. Default is 15.