gru: include ram_code in coreboot table

This is needed to ensure that the ram-code node is included in the
device tree by depthcharge.

BRANCH=none
BUG=chrome-os-partner:54566
TEST=built updated firmware, booted on kevin into Linux shell, checked
     the device tree contents:

  localhost ~ # od -tx1 /proc/device-tree/firmware/coreboot/ram-code
  0000000 00 00 00 01
  0000004
  localhost #

Change-Id: Ibe96e3bc8fc0106013241738f5726783d74bd78b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 53c002114f7044b88728c9e17150cd3a2cf1f80f
Original-Change-Id: Iba573fba9f9b88b87867c6963e48215e254319ed
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354705
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15566
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Vadim Bendebury 2016-06-21 19:07:32 -07:00 committed by Martin Roth
parent 9ae0985328
commit 1f83ffac1b
4 changed files with 19 additions and 12 deletions

View File

@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT
select RAM_CODE_SUPPORT
select RTC select RTC
select SOC_ROCKCHIP_RK3399 select SOC_ROCKCHIP_RK3399
select SPI_FLASH select SPI_FLASH

View File

@ -33,3 +33,4 @@ ramstage-y += chromeos.c
ramstage-y += mainboard.c ramstage-y += mainboard.c
ramstage-y += memlayout.ld ramstage-y += memlayout.ld
ramstage-y += reset.c ramstage-y += reset.c
ramstage-y += sdram_configs.c # Needed for ram_code()

View File

@ -59,8 +59,3 @@ uint8_t board_id(void)
adc_reading); adc_reading);
return 0; return 0;
} }
uint32_t ram_code(void)
{
return 0;
}

View File

@ -38,19 +38,29 @@ enum dram_speeds {
/* dram_928MHz = 4, */ /* dram_928MHz = 4, */
}; };
static enum dram_speeds get_sdram_index(void)
{
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
return dram_300MHz;
else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
return dram_800MHz;
else
return dram_200MHz;
}
const struct rk3399_sdram_params *get_sdram_config() const struct rk3399_sdram_params *get_sdram_config()
{ {
enum dram_speeds speed;
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) enum dram_speeds speed = get_sdram_index();
speed = dram_300MHz;
else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
speed = dram_800MHz;
else
speed = dram_200MHz;
printk(BIOS_INFO, "Using SDRAM configuration for %d MHz\n", printk(BIOS_INFO, "Using SDRAM configuration for %d MHz\n",
sdram_configs[speed].ddr_freq / (1000 * 1000)); sdram_configs[speed].ddr_freq / (1000 * 1000));
return &sdram_configs[speed]; return &sdram_configs[speed];
} }
uint32_t ram_code(void)
{
return get_sdram_index();
}