arm: Fix up new cache flush algorithm and replace dcache_*_all() with it
This patch fixes the remaining few bugs in our shiny new cache iteration by set/way/level algorithm to actually make it work: It makes it start from cache level 0 (previously it would always start at LoC and be "done" instantly), fixes up the two shifts that isolate the set bits at the end (which didn't seem to account for the fact that the first shift affects the second), and throws an S bit on that last shift so that it actually affects the conditionals after it. In addition, also moves the next_level block to the top so that we can share (and thus eliminate) some code at initialization, and turns the whole thing into a thrice-instantiated macro to create functions that fit our existing interface. Change-Id: I1338a589cbb37d74ea6e7a3d4f67ff827e24edbe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183879 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 6d94f8330191c316fe093ddb5288329453da8a4b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6932 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Julius Werner
Isaac Christensen
parent
12de698c24
commit
1f8d246d2f
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@ -35,5 +35,5 @@ libc-y += timer.c coreboot.c util.S
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libc-y += virtual.c
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libc-y += virtual.c
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libc-y += memcpy.S memset.S memmove.S
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libc-y += memcpy.S memset.S memmove.S
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libc-y += exception_asm.S exception.c
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libc-y += exception_asm.S exception.c
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libc-y += cache.c
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libc-y += cache.c cpu.S
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libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c
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libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c
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@ -36,21 +36,6 @@
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#include <arch/cache.h>
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#include <arch/cache.h>
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#include <arch/virtual.h>
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#include <arch/virtual.h>
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#define bitmask(high, low) ((1UL << (high)) + \
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((1UL << (high)) - 1) - ((1UL << (low)) - 1))
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/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */
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/* FIXME: src/include/lib.h is difficult to work with due to romcc */
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static unsigned long log2(unsigned long u)
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{
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int i = 0;
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while (u >>= 1)
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i++;
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return i;
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}
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void tlb_invalidate_all(void)
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void tlb_invalidate_all(void)
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{
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{
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/*
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/*
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@ -85,116 +70,6 @@ enum dcache_op {
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OP_DCIMVAC,
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OP_DCIMVAC,
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};
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};
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/*
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* Do a dcache operation on entire cache by set/way. This is done for
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* portability because mapping of memory address to cache location is
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* implementation defined (See note on "Requirements for operations by
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* set/way" in arch ref. manual).
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*/
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static void dcache_op_set_way(enum dcache_op op)
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{
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uint32_t ccsidr;
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unsigned int associativity, num_sets, linesize_bytes;
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unsigned int set, way;
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unsigned int level;
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level = (read_csselr() >> 1) & 0x7;
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/*
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* dcache must be invalidated by set/way for portability since virtual
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* memory mapping is system-defined. The number of sets and
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* associativity is given by CCSIDR. We'll use DCISW to invalidate the
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* dcache.
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*/
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ccsidr = read_ccsidr();
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/* FIXME: rounding up required here? */
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num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1;
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associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1;
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/* FIXME: do we need to use CTR.DminLine here? */
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linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4;
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dsb();
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/*
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* Set/way operations require an interesting bit packing. See section
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* B4-35 in the ARMv7 Architecture Reference Manual:
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*
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* A: Log2(associativity)
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* B: L+S
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* L: Log2(linesize)
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* S: Log2(num_sets)
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*
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* The bits are packed as follows:
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* 31 31-A B B-1 L L-1 4 3 1 0
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* |---|-------------|--------|-------|-----|-|
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* |Way| zeros | Set | zeros |level|0|
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* |---|-------------|--------|-------|-----|-|
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*/
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for (way = 0; way < associativity; way++) {
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for (set = 0; set < num_sets; set++) {
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uint32_t val = 0;
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val |= way << (32 - log2(associativity));
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val |= set << log2(linesize_bytes);
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val |= level << 1;
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switch(op) {
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case OP_DCCISW:
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dccisw(val);
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break;
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case OP_DCISW:
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dcisw(val);
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break;
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case OP_DCCSW:
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dccsw(val);
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break;
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default:
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break;
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}
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}
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}
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isb();
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}
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static void dcache_foreach(enum dcache_op op)
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{
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uint32_t clidr;
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int level;
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clidr = read_clidr();
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for (level = 0; level < 7; level++) {
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unsigned int ctype = (clidr >> (level * 3)) & 0x7;
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uint32_t csselr;
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switch(ctype) {
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case 0x2:
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case 0x3:
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case 0x4:
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csselr = level << 1;
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write_csselr(csselr);
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dcache_op_set_way(op);
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break;
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default:
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/* no cache, icache only, or reserved */
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break;
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}
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}
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}
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void dcache_clean_all(void)
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{
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dcache_foreach(OP_DCCSW);
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}
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void dcache_clean_invalidate_all(void)
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{
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dcache_foreach(OP_DCCISW);
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}
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void dcache_invalidate_all(void)
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{
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dcache_foreach(OP_DCISW);
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}
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unsigned int dcache_line_bytes(void)
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unsigned int dcache_line_bytes(void)
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{
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{
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uint32_t ccsidr;
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uint32_t ccsidr;
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@ -0,0 +1,117 @@
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/*
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* Optimized assembly for low-level CPU operations on ARMv7 processors.
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*
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* Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD
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*
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* Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
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* Copyright (c) 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/asm.h>
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/*
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* Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0]
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* bitfield in a register to the appropriate MCR instruction. This algorithm
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* works by initializing a bitfield with the highest-numbered set and way, and
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* generating a "set decrement" and a "way decrement". The former just contains
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* the LSB of the set field, but the latter contains the LSB of the way field
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* minus the highest valid set field... such that when you subtract it from a
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* [way:0:level] field you end up with a [way - 1:highest_set:level] field
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* through the magic of double subtraction. It's quite ingenius, really.
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* Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without
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* needing to write to memory.
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*/
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.macro dcache_apply_all crm
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dsb
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mov r3, #-2 @ initialize level so that we start at 0
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1: @next_level
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add r3, r3, #2 @ increment level
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mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
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and ip, r0, #0x07000000 @ narrow to LoC
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lsr ip, ip, #23 @ left align LoC (low 4 bits)
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cmp r3, ip @ compare
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bge 3f @done @ else fall through (r0 == CLIDR)
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add r2, r3, r3, lsr #1 @ r2 = (level << 1) * 3 / 2
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mov r1, r0, lsr r2 @ r1 = cache type
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bfc r1, #3, #28
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cmp r1, #2 @ is it data or i&d?
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blt 1b @next_level @ nope, skip level
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mcr p15, 2, r3, c0, c0, 0 @ select cache level
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isb
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mrc p15, 1, r0, c0, c0, 0 @ read CCSIDR
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ubfx ip, r0, #0, #3 @ get linesize from CCSIDR
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add ip, ip, #4 @ apply bias
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ubfx r2, r0, #13, #15 @ get numsets - 1 from CCSIDR
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lsl r2, r2, ip @ shift to set position
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orr r3, r3, r2 @ merge set into way/set/level
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mov r1, #1
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lsl r1, r1, ip @ r1 = set decr
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ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
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clz r2, ip @ number of bits to MSB of way
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lsl ip, ip, r2 @ shift by that into way position
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mov r0, #1
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lsl r2, r0, r2 @ r2 now contains the way decr
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mov r0, r3 @ get sets/level (no way yet)
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orr r3, r3, ip @ merge way into way/set/level
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bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1
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sub r2, r2, r0 @ subtract from way decr
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/* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */
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2: mcr p15, 0, r3, c7, \crm, 2 @ writeback and/or invalidate line
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cmp r3, #15 @ are we done with this level (way/set == 0)
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bls 1b @next_level @ yes, go to next level
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lsr r0, r3, #4 @ clear level bits leaving only way/set bits
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lsls r0, r0, #14 @ clear way bits leaving only set bits
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subne r3, r3, r1 @ non-zero?, decrement set #
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subeq r3, r3, r2 @ zero?, decrement way # and restore set count
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b 2b
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3: @done
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mov r0, #0 @ default back to cache level 0
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mcr p15, 2, r0, c0, c0, 0 @ select cache level
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dsb
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isb
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bx lr
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.endm
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ENTRY(dcache_invalidate_all)
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dcache_apply_all crm=c6
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ENDPROC(dcache_invalidate_all)
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ENTRY(dcache_clean_all)
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dcache_apply_all crm=c10
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ENDPROC(dcache_clean_all)
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ENTRY(dcache_clean_invalidate_all)
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dcache_apply_all crm=c14
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ENDPROC(dcache_clean_invalidate_all)
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@ -34,6 +34,7 @@ bootblock-$(CONFIG_BOOTBLOCK_SIMPLE) += bootblock_simple.c
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endif
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endif
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bootblock-y += cache.c
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bootblock-y += cache.c
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bootblock-y += cpu.S
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception_asm.S
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception_asm.S
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bootblock-y += mmu.c
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bootblock-y += mmu.c
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@ -50,6 +51,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARMV7
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ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y)
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ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y)
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romstage-y += cache.c
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romstage-y += cache.c
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romstage-y += cpu.S
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romstage-y += exception.c
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romstage-y += exception.c
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romstage-y += exception_asm.S
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romstage-y += exception_asm.S
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romstage-y += mmu.c
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romstage-y += mmu.c
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@ -66,6 +68,7 @@ endif # CONFIG_ARCH_ROMSTAGE_ARMV7
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ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV7),y)
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ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV7),y)
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ramstage-y += cache.c
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ramstage-y += cache.c
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ramstage-y += cpu.S
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ramstage-y += exception.c
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ramstage-y += exception.c
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ramstage-y += exception_asm.S
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ramstage-y += exception_asm.S
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ramstage-y += mmu.c
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ramstage-y += mmu.c
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@ -35,21 +35,6 @@
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#include <arch/cache.h>
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#include <arch/cache.h>
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#define bitmask(high, low) ((1UL << (high)) + \
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((1UL << (high)) - 1) - ((1UL << (low)) - 1))
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/* Basic log2() implementation. Note: log2(0) is 0 for our purposes. */
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/* FIXME: src/include/lib.h is difficult to work with due to romcc */
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static unsigned long log2(unsigned long u)
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{
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int i = 0;
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while (u >>= 1)
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i++;
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return i;
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}
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void tlb_invalidate_all(void)
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void tlb_invalidate_all(void)
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{
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{
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/*
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/*
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@ -84,116 +69,6 @@ enum dcache_op {
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OP_DCIMVAC,
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OP_DCIMVAC,
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};
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};
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/*
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* Do a dcache operation on entire cache by set/way. This is done for
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* portability because mapping of memory address to cache location is
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* implementation defined (See note on "Requirements for operations by
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* set/way" in arch ref. manual).
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*/
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static void dcache_op_set_way(enum dcache_op op)
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{
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uint32_t ccsidr;
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unsigned int associativity, num_sets, linesize_bytes;
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unsigned int set, way;
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unsigned int level;
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level = (read_csselr() >> 1) & 0x7;
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/*
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* dcache must be invalidated by set/way for portability since virtual
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* memory mapping is system-defined. The number of sets and
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* associativity is given by CCSIDR. We'll use DCISW to invalidate the
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* dcache.
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*/
|
|
||||||
ccsidr = read_ccsidr();
|
|
||||||
|
|
||||||
/* FIXME: rounding up required here? */
|
|
||||||
num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1;
|
|
||||||
associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1;
|
|
||||||
/* FIXME: do we need to use CTR.DminLine here? */
|
|
||||||
linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4;
|
|
||||||
|
|
||||||
dsb();
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set/way operations require an interesting bit packing. See section
|
|
||||||
* B4-35 in the ARMv7 Architecture Reference Manual:
|
|
||||||
*
|
|
||||||
* A: Log2(associativity)
|
|
||||||
* B: L+S
|
|
||||||
* L: Log2(linesize)
|
|
||||||
* S: Log2(num_sets)
|
|
||||||
*
|
|
||||||
* The bits are packed as follows:
|
|
||||||
* 31 31-A B B-1 L L-1 4 3 1 0
|
|
||||||
* |---|-------------|--------|-------|-----|-|
|
|
||||||
* |Way| zeros | Set | zeros |level|0|
|
|
||||||
* |---|-------------|--------|-------|-----|-|
|
|
||||||
*/
|
|
||||||
for (way = 0; way < associativity; way++) {
|
|
||||||
for (set = 0; set < num_sets; set++) {
|
|
||||||
uint32_t val = 0;
|
|
||||||
val |= way << (32 - log2(associativity));
|
|
||||||
val |= set << log2(linesize_bytes);
|
|
||||||
val |= level << 1;
|
|
||||||
switch(op) {
|
|
||||||
case OP_DCCISW:
|
|
||||||
dccisw(val);
|
|
||||||
break;
|
|
||||||
case OP_DCISW:
|
|
||||||
dcisw(val);
|
|
||||||
break;
|
|
||||||
case OP_DCCSW:
|
|
||||||
dccsw(val);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
isb();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void dcache_foreach(enum dcache_op op)
|
|
||||||
{
|
|
||||||
uint32_t clidr;
|
|
||||||
int level;
|
|
||||||
|
|
||||||
clidr = read_clidr();
|
|
||||||
for (level = 0; level < 7; level++) {
|
|
||||||
unsigned int ctype = (clidr >> (level * 3)) & 0x7;
|
|
||||||
uint32_t csselr;
|
|
||||||
|
|
||||||
switch(ctype) {
|
|
||||||
case 0x2:
|
|
||||||
case 0x3:
|
|
||||||
case 0x4:
|
|
||||||
csselr = level << 1;
|
|
||||||
write_csselr(csselr);
|
|
||||||
dcache_op_set_way(op);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
/* no cache, icache only, or reserved */
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void dcache_clean_all(void)
|
|
||||||
{
|
|
||||||
dcache_foreach(OP_DCCSW);
|
|
||||||
}
|
|
||||||
|
|
||||||
void dcache_clean_invalidate_all(void)
|
|
||||||
{
|
|
||||||
dcache_foreach(OP_DCCISW);
|
|
||||||
}
|
|
||||||
|
|
||||||
void dcache_invalidate_all(void)
|
|
||||||
{
|
|
||||||
dcache_foreach(OP_DCISW);
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned int dcache_line_bytes(void)
|
unsigned int dcache_line_bytes(void)
|
||||||
{
|
{
|
||||||
uint32_t ccsidr;
|
uint32_t ccsidr;
|
||||||
|
|
|
||||||
|
|
@ -30,25 +30,39 @@
|
||||||
* SUCH DAMAGE.
|
* SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <arch/asm.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These work very hard to not push registers onto the stack and to limit themselves
|
* Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0]
|
||||||
* to use r0-r3 and ip.
|
* bitfield in a register to the appropriate MCR instruction. This algorithm
|
||||||
|
* works by initializing a bitfield with the highest-numbered set and way, and
|
||||||
|
* generating a "set decrement" and a "way decrement". The former just contains
|
||||||
|
* the LSB of the set field, but the latter contains the LSB of the way field
|
||||||
|
* minus the highest valid set field... such that when you subtract it from a
|
||||||
|
* [way:0:level] field you end up with a [way - 1:highest_set:level] field
|
||||||
|
* through the magic of double subtraction. It's quite ingenius, really.
|
||||||
|
* Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without
|
||||||
|
* needing to write to memory.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* * LINTSTUB: void armv7_dcache_wbinv_all(void); */
|
.macro dcache_apply_all crm
|
||||||
ENTRY_NP(armv7_dcache_wbinv_all)
|
dsb
|
||||||
mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
|
mov r3, #-2 @ initialize level so that we start at 0
|
||||||
ands r3, r0, #0x07000000
|
|
||||||
beq .Ldone_wbinv
|
|
||||||
lsr r3, r3, #23 @ left align loc (low 4 bits)
|
|
||||||
|
|
||||||
mov r1, #0
|
1: @next_level
|
||||||
.Lstart_wbinv:
|
add r3, r3, #2 @ increment level
|
||||||
add r2, r3, r3, lsr #1 @ r2 = level * 3 / 2
|
|
||||||
|
mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
|
||||||
|
and ip, r0, #0x07000000 @ narrow to LoC
|
||||||
|
lsr ip, ip, #23 @ left align LoC (low 4 bits)
|
||||||
|
cmp r3, ip @ compare
|
||||||
|
bge 3f @done @ else fall through (r0 == CLIDR)
|
||||||
|
|
||||||
|
add r2, r3, r3, lsr #1 @ r2 = (level << 1) * 3 / 2
|
||||||
mov r1, r0, lsr r2 @ r1 = cache type
|
mov r1, r0, lsr r2 @ r1 = cache type
|
||||||
bfc r1, #3, #28
|
bfc r1, #3, #28
|
||||||
cmp r1, #2 @ is it data or i&d?
|
cmp r1, #2 @ is it data or i&d?
|
||||||
blt .Lnext_level_wbinv @ nope, skip level
|
blt 1b @next_level @ nope, skip level
|
||||||
|
|
||||||
mcr p15, 2, r3, c0, c0, 0 @ select cache level
|
mcr p15, 2, r3, c0, c0, 0 @ select cache level
|
||||||
isb
|
isb
|
||||||
|
|
@ -65,7 +79,7 @@ ENTRY_NP(armv7_dcache_wbinv_all)
|
||||||
ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
|
ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
|
||||||
clz r2, ip @ number of bits to MSB of way
|
clz r2, ip @ number of bits to MSB of way
|
||||||
lsl ip, ip, r2 @ shift by that into way position
|
lsl ip, ip, r2 @ shift by that into way position
|
||||||
mov r0, #1 @
|
mov r0, #1
|
||||||
lsl r2, r0, r2 @ r2 now contains the way decr
|
lsl r2, r0, r2 @ r2 now contains the way decr
|
||||||
mov r0, r3 @ get sets/level (no way yet)
|
mov r0, r3 @ get sets/level (no way yet)
|
||||||
orr r3, r3, ip @ merge way into way/set/level
|
orr r3, r3, ip @ merge way into way/set/level
|
||||||
|
|
@ -73,27 +87,31 @@ ENTRY_NP(armv7_dcache_wbinv_all)
|
||||||
sub r2, r2, r0 @ subtract from way decr
|
sub r2, r2, r0 @ subtract from way decr
|
||||||
|
|
||||||
/* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */
|
/* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */
|
||||||
1: mcr p15, 0, r3, c7, c14, 2 @ writeback and invalidate line
|
2: mcr p15, 0, r3, c7, \crm, 2 @ writeback and/or invalidate line
|
||||||
cmp r3, #15 @ are we done with this level (way/set == 0)
|
cmp r3, #15 @ are we done with this level (way/set == 0)
|
||||||
bls .Lnext_level_wbinv @ yes, go to next level
|
bls 1b @next_level @ yes, go to next level
|
||||||
lsl r0, r3, #10 @ clear way bits leaving only set/level bits
|
lsr r0, r3, #4 @ clear level bits leaving only way/set bits
|
||||||
lsr r0, r0, #4 @ clear level bits leaving only set bits
|
lsls r0, r0, #14 @ clear way bits leaving only set bits
|
||||||
subne r3, r3, r1 @ non-zero?, decrement set #
|
subne r3, r3, r1 @ non-zero?, decrement set #
|
||||||
subeq r3, r3, r2 @ zero?, decrement way # and restore set count
|
subeq r3, r3, r2 @ zero?, decrement way # and restore set count
|
||||||
b 1b
|
b 2b
|
||||||
|
|
||||||
.Lnext_level_wbinv:
|
3: @done
|
||||||
mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
|
|
||||||
and ip, r0, #0x07000000 @ narrow to LoC
|
|
||||||
lsr ip, ip, #23 @ left align LoC (low 4 bits)
|
|
||||||
add r3, r3, #2 @ go to next level
|
|
||||||
cmp r3, ip @ compare
|
|
||||||
blt .Lstart_wbinv @ not done, next level (r0 == CLIDR)
|
|
||||||
|
|
||||||
.Ldone_wbinv:
|
|
||||||
mov r0, #0 @ default back to cache level 0
|
mov r0, #0 @ default back to cache level 0
|
||||||
mcr p15, 2, r0, c0, c0, 0 @ select cache level
|
mcr p15, 2, r0, c0, c0, 0 @ select cache level
|
||||||
dsb
|
dsb
|
||||||
isb
|
isb
|
||||||
bx lr
|
bx lr
|
||||||
END(armv7_dcache_wbinv_all)
|
.endm
|
||||||
|
|
||||||
|
ENTRY(dcache_invalidate_all)
|
||||||
|
dcache_apply_all crm=c6
|
||||||
|
ENDPROC(dcache_invalidate_all)
|
||||||
|
|
||||||
|
ENTRY(dcache_clean_all)
|
||||||
|
dcache_apply_all crm=c10
|
||||||
|
ENDPROC(dcache_clean_all)
|
||||||
|
|
||||||
|
ENTRY(dcache_clean_invalidate_all)
|
||||||
|
dcache_apply_all crm=c14
|
||||||
|
ENDPROC(dcache_clean_invalidate_all)
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue