broadwell: Add support for ACPI \_GPE._SWS

In order to report the GPE that woke the system to the kernel
coreboot needs to keep track of the first GPE wake source and
save it in NVS so it can be returned in \_GPE._SWS method.

This is similar to the saving of PM1 status but needs to go
through all the GPE0_STS registers and check for enabled and
triggered events.

A bit of cleanup is done for areas that were touched:
- platform.asl was not formatted correctly

BUG=chrome-os-partner:8127
BRANCH=samus,auron
TEST=manual:
- suspend/resume and wake from EC event like keyboard:
ACPI _SWS is PM1 Index -1 GPE Index 112  ("special" GPIO27)
- suspend/resume and wake from RTC event:
ACPI _SWS is PM1 Index 10 GPE Index -1  (RTC)
- suspend/resume and wake from power button:
ACPI _SWS is PM1 Index 8 GPE Index -1
- suspend/resume and wake from touchpad:
ACPI _SWS is PM1 Index -1 GPE Index 13
- suspend/resume and wake from WLAN:
ACPI _SWS is PM1 Index -1 GPE Index 10

Change-Id: I574f8cd83c8bb42f420e1a00e71a23aa23195f53
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: d4e06c7dfc73f2952ce8f81263e316980aa9760f
Original-Change-Id: I9bfbbe4385f2acc2a50f41ae321b4bae262b7078
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220324
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/broadwell/acpi/globalnvs.asl

@@ -62,6 +62,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	CMEM,	32,	// 0x19 - 0x1c - CBMEM TOC
 	CBMC,	32,	// 0x1d - 0x20 - Coreboot Memory Console
 	PM1I,	32,	// 0x21 - 0x24 - PM1 wake status bit
+	GPEI,	32,	// 0x25 - 0x28 - GPE wake status bit
 
 	/* ChromeOS specific */
 	Offset (0x100),

src/soc/intel/broadwell/acpi/platform.asl

@@ -52,11 +52,12 @@ Method(TRAP, 1, Serialized)
 
 Method (_PIC, 1)
 {
-	// Remember the OS' IRQ routing choice.
+	/* Remember the OS' IRQ routing choice. */
 	Store (Arg0, PICM)
 }
 
-/* The _PTS method (Prepare To Sleep) is called before the OS is
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
  * entering a sleep state. The sleep state number is passed in Arg0
  */
 
@@ -71,8 +72,20 @@ Method(_WAK,1)
 	Return (Package (){ 0, 0 })
 }
 
+Scope (\_SB)
+{
 	Method (_SWS)
 	{
 		/* Index into PM1 for device that caused wake */
 		Return (\PM1I)
 	}
+}
+
+Scope (\_GPE)
+{
+	Method (_SWS)
+	{
+		/* Index into GPE for device that caused wake */
+		Return (\GPEI)
+	}
+}

src/soc/intel/broadwell/include/soc/nvs.h

@@ -53,7 +53,8 @@ typedef struct {
 	u32	obsolete_cmem; /* 0x19 - 0x1c - CBMEM TOC */
 	u32	cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */
 	u32	pm1i; /* 0x21 - 0x24 - PM1 wake status bit */
-	u8	rsvd3[219];
+	u32	gpei; /* 0x25 - 0x28 - GPE wake status bit */
+	u8	rsvd3[215];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;

src/soc/intel/broadwell/include/soc/pm.h

@@ -83,6 +83,8 @@
 #define TCO2_STS		0x66
 #define  TCO2_STS_SECOND_TO	(1 << 1)
 
+#define GPE0_REG_MAX		4
+#define GPE0_REG_SIZE		32
 #define GPE0_STS(x)		(0x80 + (x * 4))
 #define  GPE_31_0		0	/* 0x80/0x90 = GPE[31:0] */
 #define  GPE_63_32		1	/* 0x84/0x94 = GPE[63:32] */

src/soc/intel/broadwell/ramstage.c

@@ -28,11 +28,12 @@
 #include <soc/ramstage.h>
 #include <soc/intel/broadwell/chip.h>
 
-/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
+/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
-static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
+static void save_acpi_wake_source(global_nvs_t *gnvs)
 {
 	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
 	uint16_t pm1;
+	int gpe_reg;
 
 	if (!ps)
 		return;
@@ -50,8 +51,30 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
 	if (gnvs->pm1i >= 16)
 		gnvs->pm1i = -1;
 
-	printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n",
+	/* Scan for first set bit in GPE registers */
-	       gnvs->pm1i);
+	for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
+		u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
+		int start = gpe_reg * GPE0_REG_SIZE;
+		int end = start + GPE0_REG_SIZE;
+
+		if (gpe == 0) {
+			gnvs->gpei = end;
+			continue;
+		}
+
+		for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
+			if (gpe & 1)
+				break;
+			gpe >>= 1;
+		}
+	}
+
+	/* If unable to determine then return -1 */
+	if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
+		gnvs->gpei = -1;
+
+	printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %d GPE Index %d\n",
+	       gnvs->pm1i, gnvs->gpei);
 }
 
 static void s3_resume_prepare(void)
@@ -65,7 +88,7 @@ static void s3_resume_prepare(void)
 	if (!acpi_is_wakeup_s3())
 		memset(gnvs, 0, sizeof(global_nvs_t));
 	else
-		s3_save_acpi_wake_source(gnvs);
+		save_acpi_wake_source(gnvs);
 }
 
 void broadwell_init_pre_device(void *chip_info)