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rush: support for DMA region 

Currently rush needs a DMA region in order to communicate with
USB devices. Therefore, add that region to the memory map.

BUG=chrome-os-partner:31293
BRANCH=None
TEST=With the changes for adding non-cacheable memory range and adding DMA
region, booting from USB reaches same point as MMC.

Change-Id: I82d97840fad8cc96bf958c6efa13d2fdc1233d79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b182651a1b6db1a7adbf315b6865467590a0785c
Original-Change-Id: I6a465eaa77e0d5ab4d5fb22161e88e7a5fd9c4a8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212193
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh 2014-08-12 17:20:42 -07:00 committed by Patrick Georgi
parent 2296774af6
commit 1fb6c01688
2 changed files with 29 additions and 0 deletions
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8
src/mainboard/google/rush/Kconfig
View File

@ -95,4 +95,12 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 1
config DRAM_DMA_START
hex
default 0xc0000000
config DRAM_DMA_SIZE
hex
default 0x00200000
endif # BOARD_GOOGLE_RUSH endif # BOARD_GOOGLE_RUSH

21
src/mainboard/google/rush/mainboard.c
View File

@ -17,9 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <arch/mmu.h>
#include <device/device.h> #include <device/device.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>
#include <memrange.h>
#include <soc/clock.h> #include <soc/clock.h>
#include <soc/nvidia/tegra132/clk_rst.h> #include <soc/nvidia/tegra132/clk_rst.h>
#include <soc/nvidia/tegra132/spi.h> #include <soc/nvidia/tegra132/spi.h>
@ -86,3 +88,22 @@ struct chip_operations mainboard_ops = {
.name = "rush", .name = "rush",
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
}; };
void mainboard_add_memory_ranges(struct memranges *map)
{
/* Create non-cacheable region for DMA operations. */
memranges_insert(map, CONFIG_DRAM_DMA_START, CONFIG_DRAM_DMA_SIZE,
MA_MEM | MA_MEM_NC | MA_NS | MA_RW);
}
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
}