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pinky: Force delay for EC SPI transfers 

This gives the EC some time to wake-up between asserting /CS and
starting a transfer.

BUG=chrome-os-partner:32223
BRANCH=none
TEST=verified ~100us delay using logic analyzer on Pinky

Original-Change-Id: I9874e65abd405874c43c594d8caeeff9e1300455
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220243
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Alexandru Stan <amstan@chromium.org>
Original-Commit-Queue: Alexandru Stan <amstan@chromium.org>
Original-Tested-by: Alexandru Stan <amstan@chromium.org>

Change-Id: I103542517d3ebd7da4f0394b3ae4f68f58403b1e
(cherry picked from commit bdb67fe489b7cbea7a26492fa0536ca452434052)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9238
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
David Hendricks 2014-09-27 20:10:41 -07:00 committed by Aaron Durbin
parent 8f3883d5f4
commit 1fd5a9b36d
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/veyron_pinky/Kconfig
View File

@ -49,6 +49,10 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 0 default 0
config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
int
default 100
config VBOOT_RAMSTAGE_INDEX config VBOOT_RAMSTAGE_INDEX
hex hex
default 0x3 default 0x3