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mb/google/brya/var/agah: Enable PCIe RP 3 for LAN 

Using CLKREQ 4 and CLKSRC 4

BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage

Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Tony Huang 2022-05-09 16:15:43 +08:00 committed by Tim Wawrzynczak
parent 3f01cd1453
commit 1ffec679fe
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/brya/variants/agah/overridetree.cb
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@ -157,6 +157,12 @@ chip soc/intel/alderlake
end end
end end
device ref pcie_rp3 on device ref pcie_rp3 on
# Enable PCIE 3 using clk 4
register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/net chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)"