soc/intel/cannonlake: Change mainboard_silicon_init_params argument

Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on
xeon_sp and denverton_ns. This allows to set test config UPDs from
mainboard code as well.

Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>

src/mainboard/google/hatch/ramstage.c

@@ -8,7 +8,7 @@
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+void mainboard_silicon_init_params(FSPS_UPD *supd)
 {
 	variant_devtree_update();
 }

src/mainboard/prodrive/hermes/ramstage.c

@@ -8,8 +8,10 @@ static fsp_params parmas_list[] = {
 	/* FIXME: Fill with additional options */
 };
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+void mainboard_silicon_init_params(FSPS_UPD *supd)
 {
+	FSP_S_CONFIG *params = &supd->FspsConfig;
+
 	/* Configure pads prior to SiliconInit() in case there's any
 	   dependencies during hardware initialization. */
 	program_gpio_pads();

src/mainboard/purism/librem_cnl/ramstage.c

@@ -3,7 +3,7 @@
 #include <soc/ramstage.h>
 #include "variant.h"
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+void mainboard_silicon_init_params(FSPS_UPD *supd)
 {
 	/* Configure pads prior to SiliconInit() in case there's any
 	 * dependencies during hardware initialization. */

src/mainboard/system76/lemp9/ramstage.c

@@ -3,7 +3,7 @@
 #include <soc/ramstage.h>
 #include "gpio.h"
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+void mainboard_silicon_init_params(FSPS_UPD *supd)
 {
 	/* Configure pads prior to SiliconInit() in case there's any
 	 * dependencies during hardware initialization. */

src/soc/intel/cannonlake/fsp_params.c

@@ -143,7 +143,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Load VBT before devicetree-specific config. */
 	params->GraphicsConfigPtr = (uintptr_t)vbt_get();
 
-	mainboard_silicon_init_params(params);
+	mainboard_silicon_init_params(supd);
 
 	const struct soc_power_limits_config *soc_config;
 	soc_config = &config->power_limits_config;
@@ -527,7 +527,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 }
 
 /* Mainboard GPIO Configuration */
-__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+__weak void mainboard_silicon_init_params(FSPS_UPD *supd)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }

src/soc/intel/cannonlake/include/soc/ramstage.h

@@ -9,7 +9,7 @@
 
 #include "../../chip.h"
 
-void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void mainboard_silicon_init_params(FSPS_UPD *supd);
 void soc_init_pre_device(void *chip_info);
 
 #endif