mainboard/google/zoombini: Add config for meowth audio

Add NHLT and dt support for meowth with max98373 amp.

BUG=b:71724897
TEST='emerge-meowth coreboot' compiles correctly
TEST=check SSDT and verify entries for max98373
TEST=check NHLT ACPI tables included blobs for max98373

Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

src/mainboard/google/zoombini/Kconfig

@@ -4,6 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_ZOOMBINI
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_MAX98373
 	select DRIVERS_SPI_ACPI
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
@@ -63,6 +64,19 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
+config INCLUDE_SND_MAX98357_DA7219_NHLT
+	bool "Include blobs for audio with MAX98357_DA7219"
+	select NHLT_DMIC_4CH_16B
+	select NHLT_DMIC_2CH_16B
+	select NHLT_DA7219
+	select NHLT_MAX98357
+
+config INCLUDE_SND_MAX98373_NHLT
+	bool "Include blobs for audio with MAX98373"
+	select NHLT_DMIC_4CH_16B
+	select NHLT_DMIC_2CH_16B
+	select NHLT_MAX98373
+
 config VARIANT_DIR
 	string
 	default "meowth" if BOARD_GOOGLE_MEOWTH

src/mainboard/google/zoombini/mainboard.c

@@ -16,17 +16,44 @@
 #include <device/device.h>
 #include <ec/ec.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <nhlt.h>
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
 
 static void mainboard_init(device_t dev)
 {
 	mainboard_ec_init();
 }
 
+static unsigned long mainboard_write_acpi_tables(device_t device,
+	unsigned long current, acpi_rsdp_t *rsdp)
+{
+	uintptr_t start_addr;
+	uintptr_t end_addr;
+	struct nhlt *nhlt;
+
+	start_addr = current;
+
+	nhlt = nhlt_init();
+
+	if (nhlt == NULL)
+		return start_addr;
+
+	variant_nhlt_init(nhlt);
+
+	end_addr = nhlt_soc_serialize(nhlt, start_addr);
+
+	if (end_addr != start_addr)
+		acpi_add_table(rsdp, (void *)start_addr);
+
+	return end_addr;
+}
+
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
-	dev->ops->write_acpi_tables = NULL;
+	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/google/zoombini/variants/baseboard/Makefile.inc

@@ -19,3 +19,4 @@ romstage-y += boardid.c
 
 ramstage-y += boardid.c
 ramstage-y += gpio.c
+ramstage-y += nhlt.c

src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h

@@ -40,4 +40,8 @@ const struct lpddr4_cfg *variant_lpddr4_config(void);
 /* Return memory SKU for the board. */
 size_t variant_memory_sku(void);
 
+/* Seed the NHLT tables with the board specific information. */
+struct nhlt;
+void variant_nhlt_init(struct nhlt *nhlt);
+
 #endif /*__BASEBOARD_VARIANTS_H__ */

src/mainboard/google/zoombini/variants/baseboard/nhlt.c

@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <nhlt.h>
+#include <soc/nhlt.h>
+
+void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+{
+	/* 1-dmic configuration */
+	if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+		!nhlt_soc_add_dmic_array(nhlt, 1))
+		printk(BIOS_DEBUG, "Added 1CH DMIC array.\n");
+	/* 2-dmic configuration */
+	if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+		!nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_DEBUG, "Added 2CH DMIC array.\n");
+	/* 4-dmic configuration */
+	if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+		!nhlt_soc_add_dmic_array(nhlt, 4))
+		printk(BIOS_DEBUG, "Added 4CH DMIC array.\n");
+
+
+	if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)) {
+		/* Dialog for Headset codec. Headset codec is bi-directional
+		   but uses the same configuration settings for render and
+		   capture endpoints. */
+		if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2))
+			printk(BIOS_DEBUG, "Added Dialog_7219 codec.\n");
+
+		/* MAXIM Smart Amps for left and right speakers. */
+		if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1))
+			printk(BIOS_DEBUG, "Added Maxim_98357 codec.\n");
+	}
+
+	if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) &&
+		!nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))
+		printk(BIOS_DEBUG, "Added Maxim_98373 codec.\n");
+}

src/mainboard/google/zoombini/variants/meowth/devicetree.cb

@@ -60,6 +60,10 @@ chip soc/intel/cannonlake
 		.fall_time_ns = 38,
 	}"
 
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkSsp0" = "1"
+	register "PchHdaAudioLinkSsp1" = "1"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
@@ -82,7 +86,24 @@ chip soc/intel/cannonlake
 		end # I2C #0
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 on end # I2C #2
-		device pci 15.3 on  end # I2C #3
+		device pci 15.3 on
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "4"
+				register "imon_slot_no" = "5"
+				register "uid" = "0"
+				register "desc" = ""RIGHT SPEAKER AMP""
+				register "name" = ""MAXR""
+				device i2c 31 on end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "6"
+				register "imon_slot_no" = "7"
+				register "uid" = "1"
+				register "desc" = ""LEFT SPEAKER AMP""
+				register "name" = ""MAXL""
+				device i2c 32 on end
+			end
+		end # I2C #3
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R

src/mainboard/google/zoombini/variants/meowth/gpio.c

@@ -124,15 +124,15 @@ static const struct pad_config gpio_table[] = {
 /* ISH_I2C0_SDA */	PAD_NC(GPP_D5, NONE),
 /* ISH_I2C0_SCL */	PAD_NC(GPP_D6, NONE),
 /* ISH_I2C1_SDA */	PAD_CFG_GPO(GPP_D7, 1, DEEP), /* FCAM_RST_L */
-/* ISH_I2C1_SCL */	PAD_NC(GPP_D8, NONE),
+/* ISH_I2C1_SCL */	PAD_CFG_GPO(GPP_D8, 1, DEEP), /* DMIC_PWR_EN */
-/* ISH_SPI_CS# */	PAD_CFG_GPO(GPP_D9, 1, DEEP), /* PP3300_WLAN_EN */
+/* ISH_SPI_CS# */	PAD_NC(GPP_D9, NONE),
-/* ISH_SPI_CLK */	PAD_CFG_GPO(GPP_D10, 1, DEEP), /* FCAM_PWR_EN */
+/* ISH_SPI_CLK */	PAD_CFG_GPO(GPP_D10, 0, DEEP), /* FCAM_PWR_EN */
 /* ISH_SPI_MISO */	PAD_NC(GPP_D11, NONE),
 /* ISH_SPI_MOSI */	PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */
 /* ISH_UART0_RXD */	PAD_NC(GPP_D13, NONE), /* ISH_UART_RX */
 /* ISH_UART0_TXD */	PAD_NC(GPP_D14, NONE), /* ISH_UART_TX */
 /* ISH_UART0_RTS# */	PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TOUCHSCREEN_RST_ODL */
-/* ISH_UART0_CTS# */	PAD_CFG_GPO(GPP_D16, 0, DEEP), /* SPKR_HWRST_L */
+/* ISH_UART0_CTS# */	PAD_CFG_GPO(GPP_D16, 1, DEEP), /* SPKR_HWRST_L */
 /* DMIC_CLK1 */		PAD_CFG_NF(GPP_D17, NONE, DEEP,
 				   NF1), /* DB0_PCH_DMIC_CLK_R */
 /* DMIC_DATA1 */	PAD_CFG_NF(GPP_D18, NONE, DEEP,