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soc/intel/cannonlake: Add more HDA Audio Link settings 

Since FSP version 7.x.11.43, more HDA Audio link options are exposed,
so included that into coreboot. Users can modify that base on platform
implementations.

BUG=None
TEST=Boot up with debug build version FSP and check the debug print
result on meowth platform.

Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Lijian Zhao 2018-01-23 21:58:36 -08:00 committed by Patrick Georgi
parent e83d057c3e
commit 416ded8dc1
2 changed files with 18 additions and 0 deletions
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9
src/soc/intel/cannonlake/chip.c
View File

@ -215,6 +215,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Audio */
params->PchHdaDspEnable = config->PchHdaDspEnable;
params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {

9
src/soc/intel/cannonlake/chip.h
View File

@ -138,6 +138,15 @@ struct soc_intel_cannonlake_config {
/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
uint8_t PchHdaAudioLinkHda;
uint8_t PchHdaAudioLinkDmic0;
uint8_t PchHdaAudioLinkDmic1;
uint8_t PchHdaAudioLinkSsp0;
uint8_t PchHdaAudioLinkSsp1;
uint8_t PchHdaAudioLinkSsp2;
uint8_t PchHdaAudioLinkSndw1;
uint8_t PchHdaAudioLinkSndw2;
uint8_t PchHdaAudioLinkSndw3;
uint8_t PchHdaAudioLinkSndw4;
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];