soc/intel/apollolake: Use common systemagent code
This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
Martin Roth
parent
46a7178267
commit
208587e0f6
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@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
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select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
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select RTC
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select SMM_TSEG
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select SA_ENABLE_IMR
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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@ -63,7 +63,7 @@ ramstage-y += mmap_boot.c
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ramstage-y += p2sb.c
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ramstage-y += uart.c
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ramstage-y += nhlt.c
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ramstage-y += northbridge.c
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ramstage-y += systemagent.c
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ramstage-y += spi.c
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ramstage-y += tsc_freq.c
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ramstage-y += pmutil.c
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@ -219,7 +219,6 @@ static void set_power_limits(void)
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uint32_t power_unit;
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uint32_t tdp, min_power, max_power;
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uint32_t pl2_val;
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uint32_t *rapl_mmio_reg;
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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@ -272,15 +271,11 @@ static void set_power_limits(void)
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printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit,
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100 * (pl2_val % power_unit) / power_unit);
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/* Get the MMIO address */
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rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDRESS +
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MCHBAR_RAPL_PPL);
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/* Setting RAPL MMIO register for Power limits.
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* RAPL driver is using MSR instead of MMIO.
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* So, disabled LIMIT_EN bit for MMIO. */
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write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN));
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write32(rapl_mmio_reg + 1, limit.hi & ~(PKG_POWER_LIMIT_EN));
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MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN;
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MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN;
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}
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static void soc_init(void *data)
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@ -20,17 +20,12 @@
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#include <intelblocks/systemagent.h>
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/* IMR registers are found under MCHBAR. */
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#define MCHBAR_IMR0BASE 0x6870
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#define MCHBAR_IMR0MASK 0x6874
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#define MCH_IMR_PITCH 0x20
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#define MCH_NUM_IMRS 20
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/* RAPL Package Power Limit register under MCHBAR. */
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#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
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#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18
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#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000
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#define BIOS_RESET_CPL 0x7078
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#define PCODE_INIT_DONE (1 << 8)
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#define MCHBAR_RAPL_PPL 0x70A8
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#define CORE_DISABLE_MASK 0x7168
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@ -1,174 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <soc/iomap.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/systemagent.h>
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static uint32_t get_bar(device_t dev, unsigned int index)
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{
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uint32_t bar;
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bar = pci_read_config32(dev, index);
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/* If not enabled return 0 else strip enabled bit */
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return (bar & 1) ? (bar & ~1) : 0;
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}
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static int mc_add_fixed_mmio_resources(device_t dev, int index)
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{
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unsigned long addr;
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/* PCI extended config region */
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addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB;
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mmio_resource(dev, index++, addr, CONFIG_SA_PCIEX_LENGTH / KiB);
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/* Memory Controller Hub */
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addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB;
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mmio_resource(dev, index++, addr, MCH_BASE_SIZE / KiB);
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return index;
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}
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static bool is_imr_enabled(uint32_t imr_base_reg)
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{
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return !!(imr_base_reg & (1 << 31));
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}
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static void imr_resource(device_t dev, int idx, uint32_t base, uint32_t mask)
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{
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uint32_t base_k, size_k;
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/* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */
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base_k = (base & 0x0fffffff);
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/* Bits 28:0 encode the AND mask used for comparison, in KiB. */
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size_k = ((~mask & 0x0fffffff) + 1);
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/*
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* IMRs sit in lower DRAM. Mark them cacheable, otherwise we run
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* out of MTRRs. Memory reserved by IMRs is not usable for host
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* so mark it reserved.
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*/
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reserved_ram_resource(dev, idx, base_k, size_k);
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}
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static int mc_add_imr_resources(device_t dev, int index)
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{
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uint8_t *mchbar;
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size_t i, imr_offset;
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uint32_t base, mask;
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mchbar = (void *)(ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB));
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for (i = 0; i < MCH_NUM_IMRS; i++) {
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imr_offset = i * MCH_IMR_PITCH;
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base = read32(mchbar + imr_offset + MCHBAR_IMR0BASE);
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mask = read32(mchbar + imr_offset + MCHBAR_IMR0MASK);
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if (is_imr_enabled(base))
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imr_resource(dev, index++, base, mask);
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}
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return index;
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}
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static int mc_add_dram_resources(device_t dev, int index)
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{
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unsigned long base_k, size_k;
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uint32_t bgsm, bdsm, tolud, tseg;
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uint64_t touud;
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bgsm = ALIGN_DOWN(pci_read_config32(dev, BGSM), MiB);
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bdsm = ALIGN_DOWN(pci_read_config32(dev, BDSM), MiB);
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tolud = ALIGN_DOWN(pci_read_config32(dev, TOLUD), MiB);
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tseg = ALIGN_DOWN(pci_read_config32(dev, TSEG), MiB);
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/* TOUUD is naturally a 64 bit integer */
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touud = pci_read_config32(dev, TOUUD + sizeof(uint32_t));
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touud <<= 32;
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touud |= ALIGN_DOWN(pci_read_config32(dev, TOUUD), MiB);
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/* 0 -> 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */
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ram_resource(dev, index++, 0, 640);
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/* 0xa0000 - 0xbffff: legacy VGA */
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mmio_resource(dev, index++, 640, 128);
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/* 0xc0000 -> 0xfffff: leave without e820 entry, as it has special uses
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* 0x100000 -> top_of_ram
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*/
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base_k = 1024;
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size_k = (tseg / KiB) - base_k;
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ram_resource(dev, index++, base_k, size_k);
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/* TSEG -> BGSM */
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reserved_ram_resource(dev, index++, tseg / KiB, (bgsm - tseg) / KiB);
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/* BGSM -> BDSM */
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mmio_resource(dev, index++, bgsm / KiB, (bdsm - bgsm) / KiB);
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/* BDSM -> TOLUD */
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mmio_resource(dev, index++, bdsm / KiB, (tolud - bdsm) / KiB);
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/* 4G -> TOUUD */
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base_k = 4ULL*GiB / KiB;
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size_k = (touud / KiB) - base_k;
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ram_resource(dev, index++, base_k, size_k);
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return index;
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}
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static void northbridge_read_resources(device_t dev)
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{
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int index = 0;
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/* Read standard PCI resources. */
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pci_dev_read_resources(dev);
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/* Add all fixed MMIO resources. */
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index = mc_add_fixed_mmio_resources(dev, index);
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/* Calculate and add DRAM resources. */
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index = mc_add_dram_resources(dev, index);
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/* Add the isolated memory ranges (IMRs). */
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mc_add_imr_resources(dev, index);
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}
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static struct device_operations northbridge_ops = {
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.read_resources = northbridge_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = DEVICE_NOOP,
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.enable = DEVICE_NOOP
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_APL_NB,
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PCI_DEVICE_ID_INTEL_GLK_NB,
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0,
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};
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static const struct pci_driver northbridge_driver __pci_driver = {
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.ops = &northbridge_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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@ -31,6 +31,7 @@
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#include <fsp/api.h>
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#include <fsp/memmap.h>
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#include <fsp/util.h>
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#include <intelblocks/systemagent.h>
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#include <reset.h>
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#include <soc/cpu.h>
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#include <soc/intel/common/mrc_cache.h>
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@ -80,8 +81,13 @@ static uint32_t fsp_version CAR_GLOBAL;
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*/
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static void soc_early_romstage_init(void)
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{
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/* Set MCH base address and enable bit */
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pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1);
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static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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};
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/* Set Fixed MMIO addresss into PCI configuration space */
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sa_set_pci_bar(soc_fixed_pci_resources,
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ARRAY_SIZE(soc_fixed_pci_resources));
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/* Enable decoding for HPET. Needed for FSP global pointer storage */
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pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
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@ -140,12 +146,10 @@ static bool punit_init(void)
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* Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
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* Enable all cores here.
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*/
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write32((void *)(MCH_BASE_ADDRESS + CORE_DISABLE_MASK), 0x0);
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void *bios_rest_cpl = (void *)(MCH_BASE_ADDRESS + BIOS_RESET_CPL);
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MCHBAR32(CORE_DISABLE_MASK) = 0x0;
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/* P-Unit bring up */
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reg = read32(bios_rest_cpl);
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reg = MCHBAR32(BIOS_RESET_CPL);
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if (reg == 0xffffffff) {
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/* P-unit not found */
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printk(BIOS_DEBUG, "Punit MMIO not available\n");
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@ -155,31 +159,32 @@ static bool punit_init(void)
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pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2);
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/* Set PUINT IRQ to 24 and INTPIN LOCK */
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write32((void *)(MCH_BASE_ADDRESS + PUNIT_THERMAL_DEVICE_IRQ),
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PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
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PUINT_THERMAL_DEVICE_IRQ_LOCK);
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MCHBAR32(PUNIT_THERMAL_DEVICE_IRQ) =
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PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
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PUINT_THERMAL_DEVICE_IRQ_LOCK;
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data = read32((void *)(MCH_BASE_ADDRESS + 0x7818));
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data = MCHBAR32(0x7818);
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data &= 0xFFFFE01F;
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data |= 0x20 | 0x200;
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write32((void *)(MCH_BASE_ADDRESS + 0x7818), data);
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MCHBAR32(0x7818) = data;
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/* Stage0 BIOS Reset Complete (RST_CPL) */
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write32(bios_rest_cpl, 0x1);
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enable_bios_reset_cpl();
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/*
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* Poll for bit 8 in same reg (RST_CPL).
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* Poll for bit 8 to check if PCODE has completed its action
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* in reponse to BIOS Reset complete.
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* We wait here till 1 ms for the bit to get set.
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*/
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stopwatch_init_msecs_expire(&sw, 1);
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while (!(read32(bios_rest_cpl) & 0x100)) {
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while (!(MCHBAR32(BIOS_RESET_CPL) & PCODE_INIT_DONE)) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_DEBUG,
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"Failed to set RST_CPL bit\n");
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printk(BIOS_DEBUG, "PCODE Init Done Failure\n");
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return false;
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}
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udelay(100);
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}
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return true;
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}
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@ -0,0 +1,40 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/systemagent.h>
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Mmeory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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}
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