Apply locked MSR check to all BDW-DE platforms
It was initially applied to Wedge100 and MonoLake in CB:30290
and the issue has now been observed on Watson as well.
Original change: [CB:30290][commit 817994c1be
]
Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Change-Id: Ica9557ff159321abed55f9402aee626f18fe526b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
1474ddb722
commit
2085d6f46a
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@ -19,9 +19,6 @@
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <drivers/vpd/vpd.h>
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#include <drivers/vpd/vpd.h>
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#include <cpu/x86/msr.h>
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/lpc.h>
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#include <soc/lpc.h>
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@ -193,20 +190,7 @@ static const struct gpio_config gpio_tables[] = {
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*/
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*/
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void early_mainboard_romstage_entry(void)
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void early_mainboard_romstage_entry(void)
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{
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{
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/*
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* Sometimes the system boots in an invalid state, where random values
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* have been written to MSRs and then the MSRs are locked.
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* Seems to always happen on warm reset.
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*
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* Power cycling or a board_reset() isn't sufficient in this case, so
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* issue a full_reset() to "fix" this issue.
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*/
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msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
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if (msr.lo & 1) {
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console_init();
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printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
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full_reset();
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}
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}
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}
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/**
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/**
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@ -17,9 +17,6 @@
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#include <stddef.h>
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#include <stddef.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <cpu/x86/msr.h>
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/lpc.h>
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#include <soc/lpc.h>
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@ -44,25 +41,6 @@ void early_mainboard_romstage_entry(void)
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if (CONFIG(CONSOLE_SERIAL))
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if (CONFIG(CONSOLE_SERIAL))
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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/*
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* Sometimes the system boots in an invalid state, where random values
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* have been written to MSRs and then the MSRs are locked.
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* Seems to always happen on warm reset.
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*
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* Power cycling or a board_reset() isn't sufficient in this case, so
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* issue a full_reset() to "fix" this issue.
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*
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* It seems to be a deficiency in the reset logic, as other
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* FSP broadwell DE boards are not affected.
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*/
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msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
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if (msr.lo & 1) {
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console_init();
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printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
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full_reset();
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}
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}
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}
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/**
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/**
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@ -21,8 +21,10 @@
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#include <cbmem.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <console/usb.h>
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#include <console/usb.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/x86/smm.h>
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#include <cf9_reset.h>
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#include <program_loading.h>
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#include <program_loading.h>
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#include <timestamp.h>
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#include <timestamp.h>
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#include <version.h>
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#include <version.h>
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@ -125,7 +127,24 @@ static void early_iio_hide(void)
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iio_hide(dev);
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iio_hide(dev);
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}
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}
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}
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}
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}
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static void check_msr_lock(void)
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{
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/*
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* Sometimes the system boots in an invalid state, where random values
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* have been written to MSRs and then the MSRs are locked.
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* Seems to always happen on warm reset.
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*
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* Power cycling or a board_reset() isn't sufficient in this case, so
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* issue a full_reset() to "fix" this issue.
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*/
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msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
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if (msr.lo & 1) {
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console_init();
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printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
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full_reset();
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}
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}
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}
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/* Entry from cache-as-ram.inc. */
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/* Entry from cache-as-ram.inc. */
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@ -146,6 +165,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
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enable_integrated_uart(CONFIG_UART_FOR_CONSOLE);
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enable_integrated_uart(CONFIG_UART_FOR_CONSOLE);
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}
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}
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check_msr_lock();
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/* Call into mainboard. */
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/* Call into mainboard. */
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post_code(0x41);
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post_code(0x41);
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early_mainboard_romstage_entry();
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early_mainboard_romstage_entry();
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