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Apply locked MSR check to all BDW-DE platforms 

It was initially applied to Wedge100 and MonoLake in CB:30290
and the issue has now been observed on Watson as well.

Original change: [CB:30290][commit 817994c1be]

Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Change-Id: Ica9557ff159321abed55f9402aee626f18fe526b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Deomid "rojer" Ryabkov 2021-02-03 17:46:29 +00:00 committed by Patrick Georgi
parent 1474ddb722
commit 2085d6f46a
3 changed files with 22 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/ocp/monolake/romstage.c
View File

@ -19,9 +19,6 @@
#include <soc/romstage.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <drivers/vpd/vpd.h>
#include <cpu/x86/msr.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
@ -193,20 +190,7 @@ static const struct gpio_config gpio_tables[] = {
*/
void early_mainboard_romstage_entry(void)
{
/*
* Sometimes the system boots in an invalid state, where random values
* have been written to MSRs and then the MSRs are locked.
* Seems to always happen on warm reset.
*
* Power cycling or a board_reset() isn't sufficient in this case, so
* issue a full_reset() to "fix" this issue.
*/
msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
if (msr.lo & 1) {
console_init();
printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
full_reset();
}
}
/**

22
src/mainboard/ocp/wedge100s/romstage.c
View File

@ -17,9 +17,6 @@
#include <stddef.h>
#include <soc/romstage.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <cpu/x86/msr.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
@ -44,25 +41,6 @@ void early_mainboard_romstage_entry(void)
if (CONFIG(CONSOLE_SERIAL))
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/*
* Sometimes the system boots in an invalid state, where random values
* have been written to MSRs and then the MSRs are locked.
* Seems to always happen on warm reset.
*
* Power cycling or a board_reset() isn't sufficient in this case, so
* issue a full_reset() to "fix" this issue.
*
* It seems to be a deficiency in the reset logic, as other
* FSP broadwell DE boards are not affected.
*/
msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
if (msr.lo & 1) {
console_init();
printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
full_reset();
}
}
/**

21
src/soc/intel/fsp_broadwell_de/romstage/romstage.c
View File

@ -21,8 +21,10 @@
#include <cbmem.h>
#include <console/console.h>
#include <console/usb.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cf9_reset.h>
#include <program_loading.h>
#include <timestamp.h>
#include <version.h>
@ -125,7 +127,24 @@ static void early_iio_hide(void)
iio_hide(dev);
}
}
}
static void check_msr_lock(void)
{
/*
* Sometimes the system boots in an invalid state, where random values
* have been written to MSRs and then the MSRs are locked.
* Seems to always happen on warm reset.
*
* Power cycling or a board_reset() isn't sufficient in this case, so
* issue a full_reset() to "fix" this issue.
*/
msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
if (msr.lo & 1) {
console_init();
printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
full_reset();
}
}
/* Entry from cache-as-ram.inc. */
@ -146,6 +165,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
enable_integrated_uart(CONFIG_UART_FOR_CONSOLE);
}
check_msr_lock();
/* Call into mainboard. */
post_code(0x41);
early_mainboard_romstage_entry();