copied asus a8v-e_se to k8v-x
Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/389 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This commit is contained in:
Florian Zumbiehl
Rudolf Marek
parent
6a3e8d62f8
commit
2138556e2a
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@ -0,0 +1,73 @@
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if BOARD_ASUS_A8V_E_SE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_SOCKET_939
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select K8_HT_FREQ_1G_SUPPORT
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_VIA_VT8237R
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select SOUTHBRIDGE_VIA_K8T890
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select SUPERIO_WINBOND_W83627EHG
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_TABLES
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select HAVE_MP_TABLE
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select BOARD_ROMSIZE_KB_512
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select RAMINIT_SYSINFO
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select QRANK_DIMM_SUPPORT
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select SET_FIDVID
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config MAINBOARD_DIR
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string
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default asus/a8v-e_se
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config DCACHE_RAM_BASE
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hex
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default 0xcc000
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config DCACHE_RAM_SIZE
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hex
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default 0x4000
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x1000
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config APIC_ID_OFFSET
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hex
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default 0x10
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "A8V-E SE"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0
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config MAX_CPUS
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int
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default 2
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config HEAP_SIZE
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hex
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default 0x40000
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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endif # BOARD_ASUS_A8V_E_SE
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@ -0,0 +1,175 @@
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/*
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* This file is part of the coreboot project.
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*
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* Written by Stefan Reinauer <stepan@openbios.org>.
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* ACPI FADT, FACS, and DSDT table support added by
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*
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* Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
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* Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/device.h>
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#include <device/pci_ids.h>
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#include "southbridge/via/vt8237r/vt8237r.h"
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#include "southbridge/via/k8t890/k8t890.h"
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#include "northbridge/amd/amdk8/acpi.h"
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#include <cpu/amd/model_fxx_powernow.h>
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extern const unsigned char AmlCode[];
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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device_t dev;
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struct resource *res;
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dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
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if (!dev)
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return current;
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res = find_resource(dev, K8T890_MMCONFIG_MBAR);
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if (res) {
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
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current, res->base, 0x0, 0x0, 0xff);
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}
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return current;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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unsigned int gsi_base = 0x18;
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/* Create all subtables for processors. */
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current = acpi_create_madt_lapics(current);
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/* Write SB IOAPIC. */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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VT8237R_APIC_ID, IO_APIC_ADDR, 0);
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/* Write NB IOAPIC. */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
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/* IRQ9 ACPI active low. */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
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/* IRQ0 -> APIC IRQ2. */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0x0);
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/* Create all subtables for processors. */
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current = acpi_create_madt_lapic_nmis(current,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
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return current;
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}
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unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
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{
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k8acpi_write_vars();
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amd_model_fxx_generate_powernow(0, 0, 0);
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acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
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return (unsigned long) (acpigen_get_current());
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}
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unsigned long write_acpi_tables(unsigned long start)
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{
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unsigned long current;
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acpi_rsdp_t *rsdp;
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acpi_srat_t *srat;
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acpi_rsdt_t *rsdt;
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acpi_madt_t *madt;
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acpi_mcfg_t *mcfg;
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acpi_fadt_t *fadt;
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acpi_facs_t *facs;
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acpi_header_t *ssdt;
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acpi_header_t *dsdt;
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/* Align ACPI tables to 16 byte. */
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start = (start + 0x0f) & -0x10;
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current = start;
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printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
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/* We need at least an RSDP and an RSDT table. */
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rsdp = (acpi_rsdp_t *) current;
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current += sizeof(acpi_rsdp_t);
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rsdt = (acpi_rsdt_t *) current;
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current += sizeof(acpi_rsdt_t);
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/* Clear all table memory. */
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memset((void *) start, 0, current - start);
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acpi_write_rsdp(rsdp, rsdt, NULL);
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acpi_write_rsdt(rsdt);
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/* We explicitly add these tables later on: */
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printk(BIOS_DEBUG, "ACPI: * FACS\n");
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facs = (acpi_facs_t *) current;
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current += sizeof(acpi_facs_t);
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acpi_create_facs(facs);
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dsdt = (acpi_header_t *)current;
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memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
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current += dsdt->length;
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memcpy(dsdt, &AmlCode, dsdt->length);
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dsdt->checksum = 0; /* Don't trust iasl to get this right. */
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dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
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dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * FADT\n");
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fadt = (acpi_fadt_t *) current;
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current += sizeof(acpi_fadt_t);
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acpi_create_fadt(fadt, facs, dsdt);
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acpi_add_table(rsdp, fadt);
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/* If we want to use HPET timers Linux wants it in MADT. */
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printk(BIOS_DEBUG, "ACPI: * MADT\n");
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madt = (acpi_madt_t *) current;
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acpi_create_madt(madt);
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current += madt->header.length;
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acpi_add_table(rsdp, madt);
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printk(BIOS_DEBUG, "ACPI: * MCFG\n");
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mcfg = (acpi_mcfg_t *) current;
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acpi_create_mcfg(mcfg);
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current += mcfg->header.length;
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acpi_add_table(rsdp, mcfg);
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printk(BIOS_DEBUG, "ACPI: * SRAT\n");
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srat = (acpi_srat_t *) current;
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acpi_create_srat(srat);
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current += srat->header.length;
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acpi_add_table(rsdp, srat);
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/* SSDT */
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printk(BIOS_DEBUG, "ACPI: * SSDT\n");
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ssdt = (acpi_header_t *)current;
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acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
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current += ssdt->length;
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acpi_add_table(rsdp, ssdt);
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printk(BIOS_INFO, "ACPI: done.\n");
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return current;
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}
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,98 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 1 hw_scrubber
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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399 1 e 2 multi_core
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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445 1 e 1 iommu
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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8 0 DDR400
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8 1 DDR333
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8 2 DDR266
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8 3 DDR200
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9 0 off
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9 1 87.5%
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9 2 75.0%
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9 3 62.5%
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9 4 50.0%
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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checksums
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checksum 392 983 984
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@ -0,0 +1,97 @@
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chip northbridge/amd/amdk8/root_complex # Root complex
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device lapic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # CPU
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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subsystemid 0x1043 0 inherit
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chip northbridge/amd/amdk8 # mc0
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device pci 18.0 on # Northbridge
|
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/via/vt8237r # Southbridge
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register "ide0_enable" = "1" # Enable IDE channel 0
|
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register "ide1_enable" = "1" # Enable IDE channel 1
|
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register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
|
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register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
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register "fn_ctrl_lo" = "0" # Enable SB functions
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register "fn_ctrl_hi" = "0xad" # Enable SB functions
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device pci 0.0 on end # HT
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device pci f.1 on end # IDE
|
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device pci 11.0 on # LPC
|
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chip drivers/generic/generic # DIMM 0-0-0
|
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device i2c 50 on end
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end
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chip drivers/generic/generic # DIMM 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic # DIMM 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM 0-1-1
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device i2c 53 on end
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end
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chip superio/winbond/w83627ehg # Super I/O
|
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device pnp 2e.0 on # Floppy
|
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
|
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end
|
||||
device pnp 2e.2 on # Com1
|
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io 0x60 = 0x3f8
|
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2 (N/A on this board)
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io 0x60 = 0x2f8
|
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irq 0x70 = 3
|
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end
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device pnp 2e.5 off # PS/2 keyboard & mouse (off)
|
||||
end
|
||||
device pnp 2e.106 off # Serial flash interface (SFI)
|
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io 0x60 = 0x100
|
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end
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device pnp 2e.007 off # GPIO 1
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end
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device pnp 2e.107 on # Game port
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io 0x60 = 0x201
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end
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device pnp 2e.207 on # MIDI
|
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io 0x62 = 0x330
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irq 0x70 = 0xa
|
||||
end
|
||||
device pnp 2e.307 off # GPIO 6
|
||||
end
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device pnp 2e.8 off # WDTO#, PLED
|
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end
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||||
device pnp 2e.009 on # GPIO 2
|
||||
end
|
||||
device pnp 2e.109 off # GPIO 3
|
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end
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||||
device pnp 2e.209 off # GPIO 4
|
||||
end
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||||
device pnp 2e.309 on # GPIO 5
|
||||
end
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device pnp 2e.a off # ACPI
|
||||
end
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||||
device pnp 2e.b on # Hardware monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 0
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||||
end
|
||||
end
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||||
end
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||||
device pci 12.0 off end # VIA LAN (off, other chip used)
|
||||
end
|
||||
chip southbridge/via/k8t890 # "Southbridge" K8T890
|
||||
end
|
||||
end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
|
||||
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* ISA portions taken from QEMU acpi-dsdt.dsl.
|
||||
*/
|
||||
|
||||
DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
|
||||
{
|
||||
#include "northbridge/amd/amdk8/util.asl"
|
||||
|
||||
/* For now only define 2 power states:
|
||||
* - S0 which is fully on
|
||||
* - S5 which is soft off
|
||||
* Any others would involve declaring the wake up methods.
|
||||
*/
|
||||
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
|
||||
Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
|
||||
|
||||
/* Root of the bus hierarchy */
|
||||
Scope (\_SB)
|
||||
{
|
||||
/* Top PCI device */
|
||||
Device (PCI0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_ADR, 0x00)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x00)
|
||||
|
||||
External (BUSN)
|
||||
External (MMIO)
|
||||
External (PCIO)
|
||||
External (SBLK)
|
||||
External (TOM1)
|
||||
External (HCLK)
|
||||
External (SBDN)
|
||||
External (HCDN)
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0CF8, // Address Range Minimum
|
||||
0x0CF8, // Address Range Maximum
|
||||
0x01, // Address Alignment
|
||||
0x08, // Address Length
|
||||
)
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0CF8, // Address Length
|
||||
,, , TypeStatic)
|
||||
})
|
||||
/* Methods bellow use SSDT to get actual MMIO regs
|
||||
The IO ports are from 0xd00, optionally an VGA,
|
||||
otherwise the info from MMIO is used.
|
||||
*/
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
/* PCI Routing Table */
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
|
||||
Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
|
||||
Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
|
||||
Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
|
||||
Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
|
||||
Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
|
||||
Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
|
||||
Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
|
||||
Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
|
||||
Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
|
||||
Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
|
||||
Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
|
||||
Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
|
||||
Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
|
||||
Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
|
||||
Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
|
||||
Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
|
||||
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
|
||||
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
|
||||
})
|
||||
|
||||
Device (PEGG)
|
||||
{
|
||||
Name (_ADR, 0x00020000)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x02)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
|
||||
})
|
||||
}
|
||||
|
||||
Device (PEX0)
|
||||
{
|
||||
Name (_ADR, 0x00030000)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x03)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
|
||||
})
|
||||
}
|
||||
|
||||
Device (PEX1)
|
||||
{
|
||||
Name (_ADR, 0x00030001)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x04)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
|
||||
})
|
||||
}
|
||||
|
||||
Device (PEX2)
|
||||
{
|
||||
Name (_ADR, 0x00030002)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x05)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
|
||||
})
|
||||
}
|
||||
|
||||
Device (PEX3)
|
||||
{
|
||||
Name (_ADR, 0x00030003)
|
||||
Name (_UID, 0x00)
|
||||
Name (_BBN, 0x06)
|
||||
Name (_PRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
|
||||
})
|
||||
}
|
||||
|
||||
Device (ISA) {
|
||||
Name (_ADR, 0x00110000)
|
||||
|
||||
/* PS/2 keyboard (seems to be important for WinXP install) */
|
||||
Device (KBD)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
|
||||
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
|
||||
IRQNoFlags () {1}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* PS/2 mouse */
|
||||
Device (MOU)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IRQNoFlags () {12}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* PS/2 floppy controller */
|
||||
Device (FDC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0700"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () {
|
||||
IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
|
||||
IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
|
||||
IRQNoFlags () {6}
|
||||
DMA (Compatibility, NotBusMaster, Transfer8) {2}
|
||||
})
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Dummy device to hold auto generated reserved resources */
|
||||
Device(MBRS) {
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x01)
|
||||
External(_CRS) /* Resource Template in SSDT */
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("ASUS A8V-E SE Mainboard")
|
||||
};
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include "southbridge/via/vt8237r/vt8237r.h"
|
||||
#include "southbridge/via/k8t890/k8t890.h"
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LAPIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
|
||||
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
|
||||
|
||||
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
mptable_lintsrc(mc, bus_isa);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums. */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2006 AMD
|
||||
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
* Copyright (C) 2006 MSI
|
||||
* (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
|
||||
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
unsigned int get_sbdn(unsigned bus);
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
#include "lib/delay.c"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
#include "superio/winbond/w83627ehg/early_serial.c"
|
||||
#include "southbridge/via/vt8237r/early_smbus.c"
|
||||
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include <spd.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
|
||||
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
|
||||
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl) { }
|
||||
static void activate_spd_rom(const struct mem_controller *ctrl) { }
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include <reset.h>
|
||||
void soft_reset(void)
|
||||
{
|
||||
uint8_t tmp;
|
||||
|
||||
set_bios_reset();
|
||||
print_debug("soft reset \n");
|
||||
|
||||
/* PCI reset */
|
||||
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
|
||||
tmp |= 0x01;
|
||||
pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
|
||||
|
||||
while (1) {
|
||||
/* daisy daisy ... */
|
||||
hlt();
|
||||
}
|
||||
}
|
||||
|
||||
#include "southbridge/via/k8t890/early_car.c"
|
||||
#include "northbridge/amd/amdk8/amdk8.h"
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
||||
|
||||
unsigned int get_sbdn(unsigned bus)
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
|
||||
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
|
||||
return (dev >> 15) & 0x1f;
|
||||
}
|
||||
|
||||
static void sio_init(void)
|
||||
{
|
||||
u8 reg;
|
||||
|
||||
pnp_enter_ext_func_mode(SERIAL_DEV);
|
||||
/* We have 24MHz input. */
|
||||
reg = pnp_read_config(SERIAL_DEV, 0x24);
|
||||
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
|
||||
/* We have GPIO for KB/MS pin. */
|
||||
reg = pnp_read_config(SERIAL_DEV, 0x2a);
|
||||
pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
|
||||
/* We have all RESTOUT and even some reserved bits, too. */
|
||||
reg = pnp_read_config(SERIAL_DEV, 0x2c);
|
||||
pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
|
||||
pnp_exit_ext_func_mode(SERIAL_DEV);
|
||||
|
||||
pnp_enter_ext_func_mode(ACPI_DEV);
|
||||
pnp_set_logical_device(ACPI_DEV);
|
||||
/*
|
||||
* Set the delay rising time from PWROK_LP to PWROK_ST to
|
||||
* 300 - 600ms, and 0 to vice versa.
|
||||
*/
|
||||
reg = pnp_read_config(ACPI_DEV, 0xe6);
|
||||
pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
|
||||
/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
|
||||
reg = pnp_read_config(ACPI_DEV, 0xe4);
|
||||
pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
|
||||
pnp_exit_ext_func_mode(ACPI_DEV);
|
||||
|
||||
pnp_enter_ext_func_mode(GPIO_DEV);
|
||||
pnp_set_logical_device(GPIO_DEV);
|
||||
/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
|
||||
pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
|
||||
pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
|
||||
pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
|
||||
pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
|
||||
pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
|
||||
pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
|
||||
pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
|
||||
pnp_exit_ext_func_mode(GPIO_DEV);
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr[] = {
|
||||
// Node 0
|
||||
DIMM0, DIMM2, 0, 0,
|
||||
DIMM1, DIMM3, 0, 0,
|
||||
// Node 1
|
||||
DIMM4, DIMM6, 0, 0,
|
||||
DIMM5, DIMM7, 0, 0,
|
||||
};
|
||||
unsigned bsp_apicid = 0;
|
||||
int needs_reset = 0;
|
||||
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
|
||||
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
|
||||
sio_init();
|
||||
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
enable_rom_decode();
|
||||
|
||||
print_info("now booting... fallback\n");
|
||||
|
||||
/* Is this a CPU only reset? Or is this a secondary CPU? */
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0. */
|
||||
/* Allow the HT devices to be found. */
|
||||
enumerate_ht_chain();
|
||||
}
|
||||
|
||||
// FIXME why is this executed again? --->
|
||||
sio_init();
|
||||
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
enable_rom_decode();
|
||||
// <--- FIXME why is this executed again?
|
||||
|
||||
print_info("now booting... real_main\n");
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
/* Halt if there was a built in self test failure. */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_default_resource_map();
|
||||
setup_coherent_ht_domain();
|
||||
wait_all_core0_started();
|
||||
|
||||
print_info("now booting... Core0 started\n");
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
/* It is said that we should start core1 after all core0 launched. */
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
init_timer();
|
||||
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
|
||||
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
needs_reset |= k8t890_early_setup_ht();
|
||||
|
||||
if (needs_reset) {
|
||||
print_debug("ht reset -\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
|
||||
enable_fid_change();
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
/* Stop the APs so we can start them later in init. */
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl now. */
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
post_cache_as_ram();
|
||||
}
|
||||
Loading…
Reference in New Issue