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soc/intel/common/block/cse: Retrieve CSE RW FW version conditionally 

This patch introduces a newer config to store the CSE RW FW version into
the CBMEM. Prior to that CSE RW FW version was fetched unconditionally
and ended up increasing the boot time by 7ms to 20ms depending on the
SoC arch (including CSE arch).

The way to retrieve the CSE firmware version is by sending the HECI
command to read the CSE Boot Partition (BP) info. The cost of sending
HECI command to read the CSE FW version is between 7ms-20ms (depending
on the SoC architecture) hence,ensure this feature is platform specific
and only enabled for the platformthat would like to store the CSE version into the CBMEM.

TEST=Build and boot google/rex to avoid getting CSE RW FW version
to save 18ms of the boot time.

w/o this patch:
  10:start of ramstage                            722,215 (43)
  17:starting LZ4 decompress (ignore for x86)     741,415 (19,200)

w/ this patch:
  10:start of ramstage                            722,257 (43)
  17:starting LZ4 decompress (ignore for x86)     723,777 (1,520)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Subrata Banik 2023-06-22 01:00:06 +05:30
parent 051fedb8d3
commit 2172a6336a
3 changed files with 20 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/soc/intel/common/block/cse/Kconfig
View File

@ -45,6 +45,23 @@ config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented)
to make `HECI1` device disable using private configuration register (PCR) write. to make `HECI1` device disable using private configuration register (PCR) write.
config SOC_INTEL_STORE_CSE_FW_VERSION
bool
default n
depends on SOC_INTEL_CSE_LITE_SKU
help
This configuration option stores CSE RW FW version in CBMEM area.
This information can be used to identify if the CSE firmware update is successful
by comparing the currently running CSE RW firmware version against CSE version
belongs to the CONFIG_SOC_INTEL_CSE_RW_VERSION (decided statically while
building the AP FW image).
The way to retrieve the CSE firmware version is by sending the HECI command to
read the CSE Boot Partition (BP) info. The cost of sending HECI command to read
the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence,
ensure this feature is platform specific and only enabled for the platform
that would like to store the CSE version into the CBMEM.
config SOC_INTEL_STORE_ISH_FW_VERSION config SOC_INTEL_STORE_ISH_FW_VERSION
bool bool
default n default n

2
src/soc/intel/common/block/cse/cse.c
View File

@ -1438,7 +1438,7 @@ static void intel_cse_get_rw_version(void)
*/ */
static void cse_final(struct device *dev) static void cse_final(struct device *dev)
{ {
if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) if (CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION))
intel_cse_get_rw_version(); intel_cse_get_rw_version();
/* /*
* SoC user can have two options for sending EOP: * SoC user can have two options for sending EOP:

3
src/soc/intel/common/block/cse/cse_lite.c
View File

@ -1304,7 +1304,8 @@ static void ramstage_cse_misc_ops(void *unused)
cse_fw_sync(); cse_fw_sync();
/* Store the CSE RW Firmware Version into CBMEM */ /* Store the CSE RW Firmware Version into CBMEM */
cse_store_rw_fw_version(); if (CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION))
cse_store_rw_fw_version();
/* /*
* Store the ISH RW Firmware Version into CBMEM if ISH partition * Store the ISH RW Firmware Version into CBMEM if ISH partition
* is available * is available