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mb/google/rex: Correct GPSI0 muxing for pads requiring NF8 

GSPI0 pads required muxing to NF8. Support for extended
native functions was added in
commit b6c32d7fe4

BUG=b:244610269
TEST=build and booted on Rex

Change-Id: Iab4e0bc6890cd8e976c513fe87dda0da9b5f2ee0
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This commit is contained in:
Tarun Tuli 2022-09-02 15:20:22 -04:00 committed by Martin L Roth
parent 0dd3cf4534
commit 218fac1108
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/rex/variants/rex0/gpio.c
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@ -258,15 +258,15 @@ static const struct pad_config gpio_table_id0[] = {
/* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5),
/* GPP_F14 : GSPI_SOC_DO_TCHSCR_DI */
PAD_NC(GPP_F14, NONE),
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
/* GPP_F15 : [] ==> GSPI_SOC_DI_TCHSCR_DO */
PAD_NC(GPP_F15, NONE),
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
/* GPP_F16 : [] ==> GSPI_SOC_TCHSCR_CLK */
PAD_NC(GPP_F16, NONE),
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
/* GPP_F17 : [] ==> GSPI1_SOC_CS_L */
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
/* GPP_F18 : [] ==> GSPI_SOC_TCHSCR_CS_L */
PAD_NC(GPP_F18, NONE),
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
/* GPP_F19 : [] ==> GPP_F19_STRAP */
PAD_NC(GPP_F19, NONE),
/* GPP_F20 : [] ==> GPP_F20_STRAP */