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minnowmax: Tell the FSP to set TSEG to 8MB 

Minnowboard Max was broken by 
commit 454625c5 - intel/fsp_baytrail: Fix SMM/SMI
because TSEG wasn't set to 8MB by the FSP.
The default in the FSP is 1MB.

Change-Id: I2e671a6ca0240e931399920c62439c36133789aa
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7240
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Martin Roth 2014-10-28 18:57:48 -06:00 committed by Martin Roth
parent cab9efb2be
commit 21c48d27dd
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/intel/minnowmax/devicetree.cb
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@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail
register "SataMode" = "SATA_MODE_AHCI" register "SataMode" = "SATA_MODE_AHCI"
register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" register "MrcInitTsegSize" = "TSEG_SIZE_8_MB"
register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"