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southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop 

Correct mask to select bits 4-6 inclusively as per comment and use
bitwise operations while working with bits. Be sure to write back out
the data on the retrain.

Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Found-by: Clang
Reviewed-on: http://review.coreboot.org/6147
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Edward O'Callaghan 2014-06-28 15:36:57 +10:00
parent 38b98546a7
commit cab9efb2be
2 changed files with 4 additions and 2 deletions
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3
src/southbridge/amd/rs690/cmn.c
View File

@ -285,10 +285,11 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
/* set bit8=1, bit0-2=bit4-6 */
u32 tmp;
reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
tmp = (reg >> 4) && 0x3; /* get bit4-6 */
tmp = (reg >> 4) & 0x07; /* get bit4-6 */
reg &= 0xfff8; /* clear bit0-2 */
reg += tmp; /* merge */
reg |= 1 << 8;
nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
count++; /* CIM said "keep in loop"? */
} else {
res = 1;

3
src/southbridge/amd/rs780/cmn.c
View File

@ -326,10 +326,11 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
/* set bit8=1, bit0-2=bit4-6 */
u32 tmp;
reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
tmp = (reg >> 4) && 0x3; /* get bit4-6 */
tmp = (reg >> 4) & 0x07; /* get bit4-6 */
reg &= 0xfff8; /* clear bit0-2 */
reg += tmp; /* merge */
reg |= 1 << 8;
nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
count++; /* CIM said "keep in loop"? */
} else {
res = 1;