amd/stoneyridge: Remove amdlib functions from fixme.c
Convert functionality to use coreboot-centric functions and defined values. This change should have no functional effect. BUG=b:62241048 Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson
Aaron Durbin
parent
2d69d75749
commit
22bb2bee60
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@ -13,79 +13,67 @@
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/lapic_def.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/amdfam15.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/northbridge.h>
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#include <soc/southbridge.h>
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#include <agesawrapper.h>
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#include <amdlib.h>
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/*
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* Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
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* BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
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* MMIO to posted. Route all I/O to the southbridge.
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*/
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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msr_t topmem = rdmsr(TOP_MEM); /* todo: build bsp_topmem() earlier */
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uintptr_t base, limit;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xf4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
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/* The platform BIOS needs to ensure the memory ranges of SB800
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* legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and
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* ACPI) are set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
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/* last address before processor local APIC at FEE00000 */
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PciData = 0x00fedf00;
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PciData |= 1 << 7; /* set NP (non-posted) bit */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
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/* lowest NP address is HPET at FED00000 */
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PciData = (0xfed00000 >> 8) | 3;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
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base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
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limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
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pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
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pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8c);
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PciData = 0x00fecf00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
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base = (topmem.lo >> 8) | MMIO_WE | MMIO_RE;
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limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8;
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pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit);
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pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc4);
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PciData = 0x0000f000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Route all I/O downstream */
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base = 0 | IO_WE | IO_RE;
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limit = ALIGN_DOWN(0xffff, 4 * KiB);
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pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit);
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pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base);
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}
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/* Set the MMIO Configuration Base Address and Bus Range. */
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void amd_initmmio(void)
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{
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UINT64 MsrReg;
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AMD_CONFIG_PARAMS StdHeader;
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msr_t mmconf;
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msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
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int mtrr;
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mmconf.hi = 0;
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mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
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| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
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wrmsr(MMIO_CONF_BASE, mmconf);
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/*
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Set the MMIO Configuration Base Address and Bus Range onto MMIO
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configuration base Address MSR register.
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*/
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
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(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2)
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| 1;
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LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
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LibAmdMsrWrite(0x20c, &MsrReg, &StdHeader);
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MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
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LibAmdMsrWrite(0x20d, &MsrReg, &StdHeader);
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if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
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LibAmdMsrRead(0x1b, &MsrReg, &StdHeader);
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MsrReg |= 1 << 11;
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LibAmdMsrWrite(0x1b, &MsrReg, &StdHeader);
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}
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* todo: AGESA currently writes variable MTRRs. Once that is
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* corrected, un-hardcode this MTRR.
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*/
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;
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set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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}
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