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amd/stoneyridge: Remove amdlib functions from fixme.c 

Convert functionality to use coreboot-centric functions and defined
values.  This change should have no functional effect.

BUG=b:62241048

Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2017-10-27 17:46:24 -06:00 committed by Aaron Durbin
parent 2d69d75749
commit 22bb2bee60
1 changed files with 46 additions and 58 deletions
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104
src/soc/amd/stoneyridge/fixme.c
View File

@ -13,79 +13,67 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <device/device.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic_def.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam15.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pci_devs.h>
#include <soc/northbridge.h>
#include <soc/southbridge.h>
#include <agesawrapper.h> #include <agesawrapper.h>
#include <amdlib.h>
/*
* Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
* BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
* MMIO to posted. Route all I/O to the southbridge.
*/
void amd_initcpuio(void) void amd_initcpuio(void)
{ {
UINT64 MsrReg; msr_t topmem = rdmsr(TOP_MEM); /* todo: build bsp_topmem() earlier */
UINT32 PciData; uintptr_t base, limit;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xf4); pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
* legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
* ACPI) are set to non-posted regions. limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
*/ pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);
/* last address before processor local APIC at FEE00000 */
PciData = 0x00fedf00;
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
/* lowest NP address is HPET at FED00000 */
PciData = (0xfed00000 >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8c); base = (topmem.lo >> 8) | MMIO_WE | MMIO_RE;
PciData = 0x00fecf00; /* last address before non-posted range */ limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit);
LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ /* Route all I/O downstream */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc4); base = 0 | IO_WE | IO_RE;
PciData = 0x0000f000; limit = ALIGN_DOWN(0xffff, 4 * KiB);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc0); pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
} }
/* Set the MMIO Configuration Base Address and Bus Range. */
void amd_initmmio(void) void amd_initmmio(void)
{ {
UINT64 MsrReg; msr_t mmconf;
AMD_CONFIG_PARAMS StdHeader; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int mtrr;
mmconf.hi = 0;
mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
wrmsr(MMIO_CONF_BASE, mmconf);
/* /*
Set the MMIO Configuration Base Address and Bus Range onto MMIO * todo: AGESA currently writes variable MTRRs. Once that is
configuration base Address MSR register. * corrected, un-hardcode this MTRR.
*/ */
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
| 1;
LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(0x20c, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(0x20d, &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
LibAmdMsrRead(0x1b, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1b, &MsrReg, &StdHeader);
}
} }