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cpu/amd/agesa: Unify init files 

The init files for the AMD families using the AGESA platform
initialization code are quite similar. So reduce the differences, by
using the same comments, variable names, console messages, and blank
lines.

Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18507
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Paul Menzel 2017-02-27 01:26:42 +01:00 committed by Martin Roth
parent dd6f75ae6e
commit 22f32c723c
6 changed files with 10 additions and 13 deletions
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1
src/cpu/amd/agesa/family10/model_10_init.c
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@ -83,7 +83,6 @@ static void model_10_init(device_t dev)
msr.hi &= ~(1 << (46 - 32)); msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr); wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */ /* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR); msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0); msr.lo |= (1 << 0);

1
src/cpu/amd/agesa/family12/model_12_init.c
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@ -88,7 +88,6 @@ static void model_12_init(device_t dev)
msr.hi &= ~(1 << (46 - 32)); msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr); wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */ /* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR); msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0); msr.lo |= (1 << 0);

12
src/cpu/amd/agesa/family14/model_14_init.c
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@ -34,8 +34,9 @@
static void model_14_init(device_t dev) static void model_14_init(device_t dev)
{ {
u32 i; u8 i;
msr_t msr; msr_t msr;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings; u32 siblings;
#endif #endif
@ -58,11 +59,11 @@ static void model_14_init(device_t dev)
/* Set shadow WB, RdMEM, WrMEM */ /* Set shadow WB, RdMEM, WrMEM */
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
wrmsr (0x259, msr); wrmsr (0x259, msr);
msr.hi = msr.lo = 0x1e1e1e1e; msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr); wrmsr(0x250, msr);
wrmsr(0x258, msr); wrmsr(0x258, msr);
for (i = 0x268; i <= 0x26f; i++) for (msrno = 0x268; msrno <= 0x26f; i++)
wrmsr(i, msr); wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
@ -97,6 +98,7 @@ static void model_14_init(device_t dev)
msr.hi |= 1 << (33 - 32); msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
} }
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif #endif
/* DisableCf8ExtCfg */ /* DisableCf8ExtCfg */
@ -108,8 +110,6 @@ static void model_14_init(device_t dev)
msr = rdmsr(HWCR_MSR); msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0); msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr); wrmsr(HWCR_MSR, msr);
printk(BIOS_SPEW, "%s done.\n", __func__);
} }
static struct device_operations cpu_dev_ops = { static struct device_operations cpu_dev_ops = {

1
src/cpu/amd/agesa/family16kb/model_16_init.c
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@ -78,7 +78,6 @@ static void model_16_init(device_t dev)
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MCI_STATUS + (i * 4), msr);
} }
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */
setup_lapic(); setup_lapic();