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soc/intel/icelake: Allow coreboot to reserve stack for fsp

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Change-Id: I5f2d9548b8e2c7b1d154b7bad126ec7b1052231a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Aamir Bohra 2018-10-09 20:33:16 +05:30 committed by Subrata Banik
parent 49e0510d57
commit 23012a0dff
1 changed files with 2 additions and 0 deletions
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src/soc/intel/icelake/Kconfig
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@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_USES_CB_STACK
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
@ -89,6 +90,7 @@ config DCACHE_RAM_SIZE
config DCACHE_BSP_STACK_SIZE
hex
default 0x20000 if FSP_USES_CB_STACK
default 0x4000
help
The amount of anticipated stack usage in CAR by bootblock and