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mainboard/intel/icelake_rvp: Add ICL flash layout to support IFWI 1.6 

Modify flash layout to match ICL-IFWI layout for early SoC PO support

Flash Reg 0: Descriptor [0x0 - 0xFFF]
Flash Reg 1: BIOS [0x400000 - 0xFFFFFF]
Flash Reg 2: IFWI (consist of ME primary & secondary partition and PMC FW)
                  [0x81000 - 0x3FFFFF]
Flash Reg 8: EC (applicable for Intel RVP with internal EC support)
                  [0x1000 - 0x80FFF]

Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29316
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2018-10-29 11:54:19 +05:30 committed by Subrata Banik
parent 167a512d84
commit 49e0510d57
1 changed files with 16 additions and 17 deletions
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33
src/mainboard/intel/icelake_rvp/chromeos.fmd
View File

@ -1,21 +1,21 @@
FLASH@0xff000000 0x1000000 {
SI_ALL@0x0 0x380000 {
SI_ALL@0x0 0x3F0000 {
SI_DESC@0x0 0x1000
SI_EC@0x01000 0x80000
SI_ME@0x81000 0x2ff000
SI_EC@0x1000 0x80000
SI_ME@0x81000 0x36F000
}
SI_BIOS@0x380000 0xc80000 {
RW_SECTION_A@0x0 0x368000 {
SI_BIOS@0x400000 0xC00000 {
RW_SECTION_A@0x0 0x2d0000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x357fc0
RW_FWID_A@0x367fc0 0x40
FW_MAIN_A(CBFS)@0x10000 0x2bffc0
RW_FWID_A@0x2cffc0 0x40
}
RW_SECTION_B@0x368000 0x368000 {
RW_SECTION_B@0x2d0000 0x2d0000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x357fc0
RW_FWID_B@0x367fc0 0x40
FW_MAIN_B(CBFS)@0x10000 0x2bffc0
RW_FWID_B@0x2cffc0 0x40
}
RW_MISC@0x6d0000 0x30000 {
RW_MISC@0x5a0000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
@ -28,17 +28,16 @@ FLASH@0xff000000 0x1000000 {
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
SMMSTORE@0x700000 0x40000
RW_LEGACY(CBFS)@0x740000 0x1c0000
WP_RO@0x900000 0x380000 {
SMMSTORE@0x5d0000 0x40000
RW_LEGACY(CBFS)@0x610000 0x1c0000
WP_RO@0x7d0000 0x430000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x370000 {
RO_SECTION@0x4000 0x42c000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x280000
COREBOOT(CBFS)@0xf0000 0x33c000
}
}
}