AGESA boards: Add prepare_for_resume()
Use one common implementation for all AGESA platforms. Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6084 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
parent
31eff28f4f
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23b4f0c734
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@ -22,6 +22,7 @@
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/car.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cbmem.h>
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@ -142,7 +143,8 @@ void restore_mtrr(void)
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wrmsr(SYS_CFG, msr_data);
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}
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void *backup_resume(void)
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#ifdef __PRE_RAM__
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static void *backup_resume(void)
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{
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void *resume_backup_memory;
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@ -160,7 +162,7 @@ void *backup_resume(void)
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return resume_backup_memory;
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}
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void move_stack_high_mem(void)
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static void move_stack_high_mem(void)
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{
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void *high_stack;
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@ -173,6 +175,7 @@ void move_stack_high_mem(void)
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(high_stack - BSP_STACK_BASE_ADDR)
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:);
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}
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#endif
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#ifndef __PRE_RAM__
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static void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx)
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@ -306,7 +309,8 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
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}
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#endif
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void set_resume_cache(void)
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#ifdef __PRE_RAM__
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static void set_resume_cache(void)
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{
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msr_t msr;
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@ -331,14 +335,28 @@ void set_resume_cache(void)
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enable_cache();
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}
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void s3_resume(void)
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void prepare_for_resume(void)
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{
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int status;
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printk(BIOS_DEBUG, "Find resume memory location\n");
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void *resume_backup_memory = backup_resume();
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printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
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status = agesawrapper_amds3laterestore();
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if (status)
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printk(BIOS_DEBUG, "error level: %x \n", (u32) status);
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else
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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}
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#endif
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@ -27,10 +27,7 @@ typedef enum {
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} S3_DATA_TYPE;
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void restore_mtrr(void);
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void s3_resume(void);
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void *backup_resume(void);
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void set_resume_cache(void);
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void move_stack_high_mem(void);
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void prepare_for_resume(void);
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u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
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void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
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@ -41,9 +41,6 @@
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
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@ -133,27 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = (void *)backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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prepare_for_resume();
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}
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#endif
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@ -41,9 +41,6 @@
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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val = agesawrapper_amdinitmmio();
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hudson_lpc_port80();
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@ -116,27 +113,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = (void *)backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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prepare_for_resume();
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}
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#endif
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@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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/*
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* All cores: allow caching of flash chip code and data
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* (there are no cache-as-ram reliability concerns with family 14h)
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@ -145,27 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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prepare_for_resume();
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}
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#endif
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@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 val;
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u8 byte;
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device_t dev;
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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val = agesawrapper_amdinitmmio();
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hudson_lpc_port80();
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = (void *)backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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prepare_for_resume();
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}
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#endif
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@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val, t32;
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u32 *addr32;
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
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@ -157,27 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = (void *)backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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prepare_for_resume();
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}
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#endif
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@ -75,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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hudson_lpc_port80();
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#endif
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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val = agesawrapper_amdinitmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = (void *)backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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prepare_for_resume();
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}
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#endif
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@ -51,10 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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u32 val;
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msr_t msr;
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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/*
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* All cores: allow caching of flash chip code and data
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* (there are no cache-as-ram reliability concerns with family 14h)
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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prepare_for_resume();
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}
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#endif
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@ -38,9 +38,6 @@
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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val = agesawrapper_amdinitmmio();
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hudson_lpc_port80();
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = (void *)backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
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* reserved area.
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*/
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if (resume_backup_memory)
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memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
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printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
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prepare_for_resume();
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}
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#endif
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@ -66,10 +66,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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#if CONFIG_HAVE_ACPI_RESUME
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void *resume_backup_memory;
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#endif
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/*
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* All cores: allow caching of flash chip code and data
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* (there are no cache-as-ram reliability concerns with family 14h)
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@ -161,27 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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printk(BIOS_DEBUG, "passed.\n");
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post_code(0x61);
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printk(BIOS_DEBUG, "Find resume memory location\n");
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resume_backup_memory = backup_resume();
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post_code(0x62);
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printk(BIOS_DEBUG, "Move CAR stack.\n");
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move_stack_high_mem();
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printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
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post_code(0x63);
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disable_cache_as_ram();
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printk(BIOS_DEBUG, "CAR disabled.\n");
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set_resume_cache();
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/*
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* Copy the system memory that is in the ramstage area to the
|
||||
* reserved area.
|
||||
*/
|
||||
if (resume_backup_memory)
|
||||
memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
|
||||
|
||||
printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
|
||||
prepare_for_resume();
|
||||
}
|
||||
#endif /* CONFIG_HAVE_ACPI_RESUME */
|
||||
|
||||
|
|
|
@ -49,10 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
{
|
||||
u32 val;
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
void *resume_backup_memory;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* All cores: allow caching of flash chip code and data
|
||||
* (there are no cache-as-ram reliability concerns with family 14h)
|
||||
|
@ -148,27 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
printk(BIOS_DEBUG, "passed.\n");
|
||||
|
||||
post_code(0x61);
|
||||
printk(BIOS_DEBUG, "Find resume memory location\n");
|
||||
resume_backup_memory = backup_resume();
|
||||
|
||||
post_code(0x62);
|
||||
printk(BIOS_DEBUG, "Move CAR stack.\n");
|
||||
move_stack_high_mem();
|
||||
printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
|
||||
|
||||
post_code(0x63);
|
||||
disable_cache_as_ram();
|
||||
printk(BIOS_DEBUG, "CAR disabled.\n");
|
||||
set_resume_cache();
|
||||
|
||||
/*
|
||||
* Copy the system memory that is in the ramstage area to the
|
||||
* reserved area.
|
||||
*/
|
||||
if (resume_backup_memory)
|
||||
memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
|
||||
|
||||
printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
|
||||
prepare_for_resume();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
{
|
||||
u32 val;
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
void *resume_backup_memory;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* All cores: allow caching of flash chip code and data
|
||||
* (there are no cache-as-ram reliability concerns with family 14h)
|
||||
|
@ -149,27 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
printk(BIOS_DEBUG, "passed.\n");
|
||||
|
||||
post_code(0x61);
|
||||
printk(BIOS_DEBUG, "Find resume memory location\n");
|
||||
resume_backup_memory = backup_resume();
|
||||
|
||||
post_code(0x62);
|
||||
printk(BIOS_DEBUG, "Move CAR stack.\n");
|
||||
move_stack_high_mem();
|
||||
printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
|
||||
|
||||
post_code(0x63);
|
||||
disable_cache_as_ram();
|
||||
printk(BIOS_DEBUG, "CAR disabled.\n");
|
||||
set_resume_cache();
|
||||
|
||||
/*
|
||||
* Copy the system memory that is in the ramstage area to the
|
||||
* reserved area.
|
||||
*/
|
||||
if (resume_backup_memory)
|
||||
memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
|
||||
|
||||
printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
|
||||
prepare_for_resume();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
Loading…
Reference in New Issue