mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4
This change enables s0ix for tglrvp up3 and up4 platform. TEST=Built image and booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42954 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -114,6 +114,9 @@ chip soc/intel/tigerlake
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register "TcssXhciEn" = "1"
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register "TcssXhciEn" = "1"
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register "TcssAuxOri" = "0"
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register "TcssAuxOri" = "0"
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# Enable S0ix
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register "s0ix_enable" = "1"
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# D3Hot and D3Cold for TCSS
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# D3Hot and D3Cold for TCSS
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register "TcssD3HotEnable" = "1"
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register "TcssD3HotEnable" = "1"
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register "TcssD3ColdEnable" = "1"
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register "TcssD3ColdEnable" = "1"
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@ -110,6 +110,9 @@ chip soc/intel/tigerlake
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register "TcssXhciEn" = "1"
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register "TcssXhciEn" = "1"
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register "TcssAuxOri" = "0"
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register "TcssAuxOri" = "0"
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# Enable S0ix
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register "s0ix_enable" = "1"
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# D3Hot and D3Cold for TCSS
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# D3Hot and D3Cold for TCSS
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register "TcssD3HotEnable" = "1"
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register "TcssD3HotEnable" = "1"
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register "TcssD3ColdEnable" = "1"
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register "TcssD3ColdEnable" = "1"
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