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mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 

This change enables s0ix for tglrvp up3 and up4 platform.

TEST=Built image and booted to kernel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42954
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Zhao 2020-06-30 17:36:24 -07:00 committed by Patrick Georgi
parent ef079c86ea
commit 23d3ad0f64
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@ -114,6 +114,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1" register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0" register "TcssAuxOri" = "0"
# Enable S0ix
register "s0ix_enable" = "1"
# D3Hot and D3Cold for TCSS # D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1" register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1" register "TcssD3ColdEnable" = "1"

3
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -110,6 +110,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1" register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0" register "TcssAuxOri" = "0"
# Enable S0ix
register "s0ix_enable" = "1"
# D3Hot and D3Cold for TCSS # D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1" register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1" register "TcssD3ColdEnable" = "1"