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coreboot-kgpe-d16
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Change the CBFS build process to use coreboot.rom 

instead of coreboot.strip. That fixes the normal
image because the calculations for its offset in
the ROM match reality again.

This requires changes in CBFS configurations to
minimize the bootblock size. These are also done
for CBFS boards.

Other than this a couple of minor fixes are in this
patch:
- make asus/m2v-mx_se build with abuild with a
  crosscompiler
- move CONFIG_CBFS for hp/dl145_g3 to Options.lb
  as it's done everywhere else
- change the default config of abuild to not
  provide ROM_IMAGE_SIZE values for the images
  in a CBFS configuration
- change abuild's crosscompile autodetection to
  not try to use "i386-elf-i386-elf-gcc" (which
  is bogus)

Except for the latter two abuild changes (both
in util/abuild/abuild), they're available as
patch set on the mailing list in a mail from
2009-06-05 titled
[PATCH]es to get normal image to work again with CBFS

The changes in util/abuild/abuild are trivial and
abuild tested.

As discussed on the list,
targets/hp/dl145_g3/Config-abuild.lb is
deleted, now that Config.lb works again.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2009-06-06 07:19:53 +00:00
parent aa58f5427f
commit 240ef7c769
21 changed files with 43 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/config/failovercalculation.lb
View File

@ -10,8 +10,13 @@ else
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
default ROM_SECTION_OFFSET = 0
if CONFIG_CBFS
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
default ROM_SECTION_OFFSET = 0
end
end
end

9
src/config/nofailovercalculation.lb
View File

@ -6,8 +6,13 @@ if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
if CONFIG_CBFS
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end
end
##

9
src/config/nofailovercalculation128.lb
View File

@ -6,8 +6,13 @@ if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
if CONFIG_CBFS
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end
end
##

4
src/mainboard/emulation/qemu-x86/Config.lb
View File

@ -3,14 +3,14 @@
## (coreboot plus bootloader) will live in the boot rom chip.
##
default ROM_SIZE = 256 * 1024
default ROM_SECTION_SIZE = ROM_SIZE
default ROM_SECTION_SIZE = ROM_IMAGE_SIZE
default ROM_SECTION_OFFSET = 0
##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default PAYLOAD_SIZE = ( ROM_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##

2
src/mainboard/emulation/qemu-x86/Options.lb
View File

@ -100,7 +100,7 @@ default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default FALLBACK_SIZE = ROM_IMAGE_SIZE
##
## Use a small 8K stack

8
src/mainboard/hp/dl145_g3/Options.lb
View File

@ -121,9 +121,7 @@ default ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#256K
default FALLBACK_SIZE=0x40000
default FALLBACK_SIZE=ROM_IMAGE_SIZE
#more 1M for pgtbl
default CONFIG_LB_MEM_TOPK=2048
@ -329,5 +327,9 @@ default MAXIMUM_CONSOLE_LOGLEVEL=8
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
##
## CBFS
default CONFIG_CBFS=1
### End Options.lb
end

2
src/mainboard/kontron/986lcd-m/Options.lb
View File

@ -249,7 +249,7 @@ default HEAP_SIZE=0x8000
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=131072
default FALLBACK_SIZE=ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM

2
src/mainboard/via/vt8454c/Options.lb
View File

@ -158,7 +158,7 @@ default CONFIG_IOAPIC=1
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default FALLBACK_SIZE = ROM_IMAGE_SIZE
##
## Use a small 8K stack

4
targets/asus/m2v-mx_se/Config-abuild.lb
View File

@ -20,6 +20,10 @@
target asus_m2v-mx_se
mainboard asus/m2v-mx_se
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
## ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).

3
targets/emulation/qemu-x86/Config-abuild.lb
View File

@ -8,11 +8,8 @@ option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=256*1024
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0"
payload __PAYLOAD__
end

1
targets/emulation/qemu-x86/Config-lab.lb
View File

@ -13,7 +13,6 @@ option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=6
romimage "image"
option ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION="-LAB"
payload ../payload.elf.lzma
end

1
targets/emulation/qemu-x86/Config.OLPC.lb
View File

@ -13,7 +13,6 @@ option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=6
romimage "image"
option ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION="-OpenBIOS"
payload /tmp/olpcpayload.elf
end

1
targets/emulation/qemu-x86/Config.lb
View File

@ -11,7 +11,6 @@ option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=6
romimage "normal"
option ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION="-GRUB2"
# payload /home/stepan/core.img
payload ../payload.elf

27
targets/hp/dl145_g3/Config-abuild.lb
View File

@ -1,27 +0,0 @@
# This will make a target directory of ./VENDOR_MAINBOARD
target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=1024*(1024-32)
option FALLBACK_SIZE=1024*512
option CONFIG_CBFS = 1
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "fallback"

2
targets/hp/dl145_g3/Config.lb
View File

@ -25,11 +25,9 @@ target dl145_g3
mainboard hp/dl145_g3
option ROM_SIZE= 1024*1024
option CONFIG_CBFS = 1
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
payload ./bios.bin.elf

3
targets/kontron/986lcd-m/Config-abuild.lb
View File

@ -11,18 +11,15 @@ __COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=1024*1024
option FALLBACK_SIZE=1024*64
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end

12
targets/kontron/986lcd-m/Config.lb
View File

@ -5,20 +5,8 @@ mainboard kontron/986lcd-m
## (normal AND fallback images and payloads).
option ROM_SIZE = 1024 * 1024
# Use this line instead if you want to use onboard VGA:
# option ROM_SIZE = (1024 * 1024) - (64 * 1024)
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE = 128 * 1024
## FALLBACK_SIZE is the amount of the ROM the complete fallback image
## (including payload) will use.
option FALLBACK_SIZE = ROM_SIZE
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 144 * 1024
payload ../payload.elf
end

2
targets/via/vt8454c/Config-abuild.lb
View File

@ -29,14 +29,12 @@ option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option ROM_SIZE=512*1024
option FALLBACK_SIZE=512*1024
__COMPRESSION__
__LOGLEVEL__
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x15000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end

2
targets/via/vt8454c/Config.lb
View File

@ -30,14 +30,12 @@ option ROM_SIZE=(512-64)*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x14000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload $(HOME)/payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x14000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload $(HOME)/payload.elf
end

7
util/abuild/abuild
View File

@ -176,14 +176,20 @@ EOF
cat <<EOF
romimage "normal"
option USE_FALLBACK_IMAGE=0
if CONFIG_CBFS
else
option ROM_IMAGE_SIZE=0x17000
end
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
if CONFIG_CBFS
else
option ROM_IMAGE_SIZE=0x17000
end
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
@ -375,6 +381,7 @@ function build_target
CC="$CC -Wa,--divide"
fi
CROSS_COMPILE="$TARCH-elf-"
CC=gcc
echo using $CROSS_COMPILE$CC
found_crosscompiler=true
fi

2
util/newconfig/config.g
View File

@ -2293,7 +2293,7 @@ def writemakefile(path):
# build the bootblock here.
file.write("\n\tcat")
for j in i.roms:
file.write(" %s/coreboot.strip " % j)
file.write(" %s/coreboot.rom " % j)
file.write("> %s.bootblock\n\n" %i.name)
file.write("\t./cbfstool %s create %s %s %s.bootblock\n"
%(i.name, romsize, bootblocksize, i.name))