240ef7c769
instead of coreboot.strip. That fixes the normal image because the calculations for its offset in the ROM match reality again. This requires changes in CBFS configurations to minimize the bootblock size. These are also done for CBFS boards. Other than this a couple of minor fixes are in this patch: - make asus/m2v-mx_se build with abuild with a crosscompiler - move CONFIG_CBFS for hp/dl145_g3 to Options.lb as it's done everywhere else - change the default config of abuild to not provide ROM_IMAGE_SIZE values for the images in a CBFS configuration - change abuild's crosscompile autodetection to not try to use "i386-elf-i386-elf-gcc" (which is bogus) Except for the latter two abuild changes (both in util/abuild/abuild), they're available as patch set on the mailing list in a mail from 2009-06-05 titled [PATCH]es to get normal image to work again with CBFS The changes in util/abuild/abuild are trivial and abuild tested. As discussed on the list, targets/hp/dl145_g3/Config-abuild.lb is deleted, now that Config.lb works again. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
29 lines
627 B
Text
29 lines
627 B
Text
# This will make a target directory of ./VENDOR_MAINBOARD
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target VENDOR_MAINBOARD
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mainboard VENDOR/MAINBOARD
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option CC="CROSSCC"
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option CROSS_COMPILE="CROSS_PREFIX"
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option HOSTCC="CROSS_HOSTCC"
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__COMPRESSION__
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__LOGLEVEL__
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option ROM_SIZE=1024*1024
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romimage "normal"
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option USE_FALLBACK_IMAGE=0
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option COREBOOT_EXTRA_VERSION=".0-normal"
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payload __PAYLOAD__
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end
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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option COREBOOT_EXTRA_VERSION=".0-fallback"
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payload __PAYLOAD__
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end
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buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
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#pci_rom ../../../misc/kontron-pci8086,27a2.rom vendor_id=0x8086 device_id=0x27a2
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