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soc/amd/common/block/smbus: refactor fch_smbus_init 

Move the setup of the base address to a separate function and explicitly
set the SMBUS and ASF I/O port decode even though it is expected to
already be set after reset.

Change-Id: I8072ab78985021d19b6528100c674ecdd777e62e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2020-12-07 23:30:04 +01:00
parent 6b519b230e
commit 240f99c1c3
2 changed files with 14 additions and 4 deletions
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4
src/soc/amd/common/block/include/amdblocks/acpimmio.h
View File

@ -15,12 +15,12 @@
* newer SoCs, but not for the generations with separate FCH or Kabini.
*/
#define PM_DECODE_EN 0x00
#define SMBUS_ASF_IO_BASE_SHIFT 8
#define SMBUS_ASF_IO_BASE_MASK (0xff << SMBUS_ASF_IO_BASE_SHIFT)
#define SMBUS_ASF_IO_EN (1 << 4)
#define CF9_IO_EN (1 << 1)
#define LEGACY_IO_EN (1 << 0)
#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */
/*
* Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs
* and the Kabini SoC fall into this category. Kabini's successor, Mullins, uses

14
src/soc/amd/common/block/smbus/smbus_early_fch.c
View File

@ -3,14 +3,24 @@
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/smbus.h>
#include <soc/southbridge.h>
#include <soc/iomap.h>
static void fch_smbus_enable_decode(uint16_t base)
{
uint32_t val = pm_read32(PM_DECODE_EN);
/* Configure upper byte of the I/O address; lower byte is always 0 */
val = (val & ~SMBUS_ASF_IO_BASE_MASK) | (base & SMBUS_ASF_IO_BASE_MASK);
/* Set enable decode bit even though it should already be set */
val |= SMBUS_ASF_IO_EN;
pm_write32(PM_DECODE_EN, val);
}
void fch_smbus_init(void)
{
/* 400 kHz smbus speed. */
const uint8_t smbus_speed = (66000000 / (400000 * 4));
pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
fch_smbus_enable_decode(SMB_BASE_ADDR);
smbus_write8(SMBTIMING, smbus_speed);
/* Clear all SMBUS status bits */
smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);