Revert "mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants"

This reverts commit 2b19d547c0.

A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.

For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.

BUG=b:240669428
TEST=verify that EPP is back to the by default 50% setting
     `iotools rdmsr 0 0x774'

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I76d3914e51c5320af4c202558e1e7c57b7c0de54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>

src/mainboard/intel/adlrvp/devicetree.cb

@@ -170,10 +170,6 @@ chip soc/intel/alderlake
 
 	register "cnvi_bt_audio_offload" = "true"
 
-	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
-	register "enable_energy_perf_pref" = "true"
-	register "energy_perf_pref_value" = "0x73"
-
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.i2c[0] = {

src/mainboard/intel/adlrvp/devicetree_m.cb

@@ -143,10 +143,6 @@ chip soc/intel/alderlake
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "1"
 
-	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
-	register "enable_energy_perf_pref" = "true"
-	register "energy_perf_pref_value" = "0x73"
-
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.gspi[1] = {

src/mainboard/intel/adlrvp/devicetree_n.cb

@@ -116,10 +116,6 @@ chip soc/intel/alderlake
 
 	register "cnvi_bt_audio_offload" = "true"
 
-	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
-	register "enable_energy_perf_pref" = "true"
-	register "energy_perf_pref_value" = "0x73"
-
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.i2c[0] = {