GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA fam14: Increase MMCONF region 

Increase to max 64 buses, as there are no benefits of limit 16.

NOTE: It appears there is no matching (early) programming of the
region to non-posted MMIO.

Change-Id: I664789f7bd90992840e5817555cd3621c2d1e86c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7813
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki 2014-12-14 16:36:09 +02:00
parent af87020f0a
commit 24e31e28c4
2 changed files with 2 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/amd/agesa/family14/Kconfig
View File

@ -37,6 +37,6 @@ config MMCONF_BASE_ADDRESS
config MMCONF_BUS_NUMBER
int
default 16
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY14

17
src/northbridge/amd/agesa/family14/agesawrapper.c
View File

@ -34,8 +34,6 @@
#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
/* Define AMD Ontario APPU SSID/SVID */
#define AMD_APU_SVID 0x1022
#define AMD_APU_SSID 0x1234
@ -102,24 +100,11 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64) (BusRangeVal << 2) | MMCONF_ENABLE);
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*