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vc/amd/fsp/cezanne:Add s0i_enable upd control 

Add upd to enable S0i3 in fsp.

BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.

Cq-Depend: chrome-internal:3777391
Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Jason Glenesk 2021-04-22 05:00:32 -07:00 committed by Patrick Georgi
parent b1e8a8a6ce
commit 250e610fa0
1 changed files with 2 additions and 1 deletions
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3
src/vendorcode/amd/fsp/cezanne/FspmUpd.h
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@ -100,7 +100,8 @@ typedef struct __packed {
/** Offset 0x04A4**/ uint8_t fch_ioapic_id;
/** Offset 0x04A5**/ uint8_t sata_enable;
/** Offset 0x04A6**/ uint8_t fch_reserved[32];
/** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[58];
/** Offset 0x04A7**/ uint8_t s0i3_enable;
/** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[57];
/** Offset 0x0500**/ uint16_t UpdTerminator;
} FSP_M_CONFIG;