M4A785T-M: fix TOM2.
This commit is based on the commit 94fa3db366
(AMD Mahogany Fam10 ACPI table fixes.)
With commit permit to boot without pci=nocrs on the M4A785T-M board.
Before the fix dmesg contained the following:
[ 0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
(20110112/psargs-359)
[ 0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
(20110112/psargs-359)
[ 0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
(20110112/psargs-359)
Now it only contains:
[ 0.312102] TOM: 0000000080000000 aka 2048M
Change-Id: I5d517604abe938af19b70d57d92c1f973114c1cd
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/635
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Denis 'GNUtoo' Carikli
Marc Jones
parent
131c936b45
commit
250f655127
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@ -36,7 +36,7 @@ DefinitionBlock (
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Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
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Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
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Name(PBLN, 0x0) /* Length of BIOS area */
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Name(PBLN, 0x0) /* Length of BIOS area */
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Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
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Name(PCBA,CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
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Name(HPBA, 0xFED00000) /* Base address of HPET table */
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Name(HPBA, 0xFED00000) /* Base address of HPET table */
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Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
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Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
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@ -1421,21 +1421,6 @@ DefinitionBlock (
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IRQNoFlags(){13}
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IRQNoFlags(){13}
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})
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})
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} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
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} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
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Device(HPTM) {
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Name(_HID,EISAID("PNP0103"))
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Name(CRS,ResourceTemplate() {
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Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
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})
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Method(_STA, 0) {
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Return(0x0F) /* sata is visible */
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}
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Method(_CRS, 0) {
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CreateDwordField(CRS, ^HPT._BAS, HPBA)
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Store(HPBA, HPBA)
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Return(CRS)
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}
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} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
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} /* end LIBR */
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} /* end LIBR */
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Device(HPBR) {
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Device(HPBR) {
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@ -1546,88 +1531,26 @@ DefinitionBlock (
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Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
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Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
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Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
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Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
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Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
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/* memory space for PCI BARs below 4GB */
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Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
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Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
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/* DRAM Memory from 1MB to TopMem */
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Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
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/* BIOS space just below 4GB */
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DWORDMemory(
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ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00, /* Granularity */
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0x00000000, /* Min */
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0x00000000, /* Max */
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0x00000000, /* Translation */
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0x00000001, /* Max-Min, RLEN */
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,,
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PCBM
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)
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/* DRAM memory from 4GB to TopMem2 */
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QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, /* Granularity */
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0x00000000, /* Min */
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0x00000000, /* Max */
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0x00000000, /* Translation */
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0x00000001, /* Max-Min, RLEN */
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,,
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DMHI
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)
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/* BIOS space just below 16EB */
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QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, /* Granularity */
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0x00000000, /* Min */
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0x00000000, /* Max */
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0x00000000, /* Translation */
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0x00000001, /* Max-Min, RLEN */
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,,
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PEBM
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)
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}) /* End Name(_SB.PCI0.CRES) */
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}) /* End Name(_SB.PCI0.CRES) */
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Method(_CRS, 0) {
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Method(_CRS, 0) {
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/* DBGO("\\_SB\\PCI0\\_CRS\n") */
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/* DBGO("\\_SB\\PCI0\\_CRS\n") */
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CreateDWordField(CRES, ^MMIO._BAS, MM1B)
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CreateDWordField(CRES, ^EMM1._BAS, EM1B)
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CreateDWordField(CRES, ^MMIO._LEN, MM1L)
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CreateDWordField(CRES, ^EMM1._LEN, EM1L)
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CreateDWordField(CRES, ^DMLO._BAS, DMLB)
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CreateDWordField(CRES, ^DMLO._LEN, DMLL)
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CreateDWordField(CRES, ^PCBM._MIN, PBMB)
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CreateDWordField(CRES, ^PCBM._LEN, PBML)
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CreateQWordField(CRES, ^DMHI._MIN, DMHB)
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CreateQWordField(CRES, ^DMHI._LEN, DMHL)
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CreateQWordField(CRES, ^PEBM._MIN, EBMB)
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CreateQWordField(CRES, ^PEBM._LEN, EBML)
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If(LGreater(LOMH, 0xC0000)){
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Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
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Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
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}
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/* Set size of memory from 1MB to TopMem */
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Subtract(TOM1, 0x100000, DMLL)
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/*
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/*
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* If(LNotEqual(TOM2, 0x00000000)){
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* Declare memory between TOM1 and 4GB as available
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* Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
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* for PCI MMIO.
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* ShiftLeft(TOM2, 20, Local0)
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* Use ShiftLeft to avoid 64bit constant (for XP).
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* Subtract(Local0, 0x100000000, DMHL)
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* This will work even if the OS does 32bit arithmetic, as
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* }
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* 32bit (0x00000000 - TOM1) will wrap and give the same
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* result as 64bit (0x100000000 - TOM1).
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*/
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*/
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Store(TOM1, MM1B)
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/* If there is no memory above 4GB, put the BIOS just below 4GB */
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ShiftLeft(0x10000000, 4, Local0)
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If(LEqual(TOM2, 0x00000000)){
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Subtract(Local0, TOM1, Local0)
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Store(PBAD,PBMB) /* Reserve the "BIOS" space */
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Store(Local0, MM1L)
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Store(PBLN,PBML)
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}
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Else { /* Otherwise, put the BIOS just below 16EB */
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ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
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Store(PBLN,EBML)
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}
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Return(CRES) /* note to change the Name buffer */
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Return(CRES) /* note to change the Name buffer */
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} /* end of Method(_SB.PCI0._CRS) */
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} /* end of Method(_SB.PCI0._CRS) */
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