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soc/amd/stoneyridge: Add definition for GENINT_DISABLE 

BUG=b:71867096
TEST=None

Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2018-01-11 16:14:39 -08:00
parent 883de54fed
commit 2572153aef
1 changed files with 1 additions and 0 deletions
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1
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -93,6 +93,7 @@
#define PM_HUD_SD_FLASH_CTRL 0xe7 #define PM_HUD_SD_FLASH_CTRL 0xe7
#define PM_YANG_SD_FLASH_CTRL 0xe8 #define PM_YANG_SD_FLASH_CTRL 0xe8
#define PM_PCIB_CFG 0xea #define PM_PCIB_CFG 0xea
#define PM_GENINT_DISABLE BIT(0)
#define PM_LPC_GATING 0xec #define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1) #define PM_LPC_A20_EN BIT(1)