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mb/google/drallion: Clean up unused weak function 

Drallion only supports on board dimm. Remove the spd read from
SMBus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function
is not needed.

BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37780
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai 2019-12-17 16:09:26 +08:00 committed by Patrick Georgi
parent 629abbe751
commit 25eb1b3149
1 changed files with 0 additions and 45 deletions
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45
src/mainboard/google/drallion/romstage.c
View File

@ -18,51 +18,6 @@
#include <soc/romstage.h>
#include <baseboard/variants.h>
void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {}
static const struct cnl_mb_cfg memcfg = {
/* Access memory info through SMBUS. */
.spd[0] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa0},
},
.spd[1] = {.read_type = NOT_EXISTING},
.spd[2] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa4},
},
.spd[3] = {.read_type = NOT_EXISTING},
/*
* The dqs_map arrays map the ddr4 pins to the SoC pins
* for both channels.
*
* the index = pin number on ddr4 part
* the value = pin number on SoC
*/
.dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7},
.dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7},
/* Baseboard uses 121, 81 and 100 rcomp resistors */
.rcomp_resistor = {121, 81, 100},
/*
* Baseboard Rcomp target values.
*/
.rcomp_targets = {100, 40, 20, 20, 26},
/* Disable Early Command Training */
.ect = 0,
/* Base on board design */
.vref_ca_config = 2,
};
const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
{
return &memcfg;
}
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
struct cnl_mb_cfg board_memcfg;