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mb/google/drallion: Remove Wilco 1.0 CML code from drallion code 

Drallion supports D3 hot not D3 cold. Remove the code which used
for Wilco 1.0 CML.

BUG=b:140068267
TEST=boot into OS without any issues
BRANCH=none

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifc83fae7ac462d3e6595742d96952c2a2607c88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Mike Wiitala <mwiitala@google.com>
This commit is contained in:
Eric Lai 2019-12-17 15:35:06 +08:00 committed by Patrick Georgi
parent f82fa746bf
commit 629abbe751
2 changed files with 4 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/mainboard/google/drallion/ramstage.c
View File

@ -59,13 +59,6 @@ void smbios_fill_dimm_locator(const struct dimm_info *dimm,
}
}
static const struct pad_config gpio_unused[] = {
/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
/* SUSACK# */ PAD_NC(GPP_A15, NONE),
/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
};
static void mainboard_init(void *chip_info)
{
const struct pad_config *gpio_table;
@ -73,10 +66,6 @@ static void mainboard_init(void *chip_info)
gpio_table = variant_gpio_table(&num_gpios);
cnl_configure_pads(gpio_table, num_gpios);
/* Disable unused pads for devices with board ID > 2 */
if (board_id() > 2)
gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
}
static void mainboard_enable(struct device *dev)

10
src/mainboard/google/drallion/variants/drallion/gpio.c
View File

@ -36,9 +36,9 @@ static const struct pad_config gpio_table[] = {
/* PME# */ PAD_NC(GPP_A11, NONE),
/* ISH_LID_CL#_TAB */
/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2),
/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP),
/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
/* ESPI_RESET# */
/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP),
/* SUSACK# */ PAD_NC(GPP_A15, NONE),
/* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */
/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
/* ISH_ACC1_INT# */
@ -200,6 +200,8 @@ static const struct pad_config gpio_table[] = {
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */
/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */
/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),
@ -226,9 +228,6 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
/* SSD RESET pin will stay low first */
/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
/* UART2_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */
/* UART2_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* SDA_PCH_H1 */
@ -240,7 +239,6 @@ static const struct pad_config early_gpio_table[] = {
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
/* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */
/* GPP_F2 */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* DDR_CHB_EN_1P8 */
/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */