arch/riscv: Only execute on hart 0 for now

Only execute coreboot on hart 0 until synchronisation between hart's is ready.
Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/riscv/bootblock.S

@@ -24,6 +24,12 @@
 .global _estack
 .globl _start
 _start:
+	csrr a0, mhartid
+	li a3, 0
+	beq a0, a3, _hart_zero
+_hart_loop:
+	j _hart_loop
+_hart_zero:
 
 	# The boot ROM may pass the following arguments to coreboot:
 	#   a0: the value of mhartid