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nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4 

Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14542
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2016-04-29 01:34:08 -05:00
parent 7f731f8d4f
commit 263c679075
2 changed files with 8 additions and 0 deletions
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4
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
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@ -1439,6 +1439,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
/* Back up the Nibble 0 delays for later use */
memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay));
}
/* Exit nibble training if current DIMM is not x4 */
if ((pDCTstat->Dimmx4Present & (1 << (dimm + Channel))) == 0)
break;
}
if (_2Ranks) {

4
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
View File

@ -184,6 +184,10 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
}
pDCTData->WLCriticalGrossDelayPrevPass = 0x0;
/* Exit nibble training if current DIMM is not x4 */
if ((pDCTstat->Dimmx4Present & (1 << (dimm + dct))) == 0)
break;
}
return 0;