Brain: Apply differences between Jerry and Brain
This applies the differences between Jerry and Brain: - No EC - No SD card - Minor changes to GPIOs (no lid, power button active low) - No variations between board IDs (yet) - No backlight/display attached, but we do have some HDMI and VOP configuration (need to double check that it's right). BUG=none BRANCH=none TEST=built and booted on Brain (requires follow-up CL to get into depthcharge) Change-Id: Idbbc19856e05a145637c28d87c3e19855d13f03b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 67151129c28ca7dd83464e5a5c183d006299293c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I3c761d3d4d186a6208a772c05193bdcbd4a5c105 Original-Reviewed-on: https://chromium-review.googlesource.com/235921 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9638 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
David Hendricks
Stefan Reinauer
parent
16e32ed2f3
commit
2646573a0b
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@ -24,16 +24,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select BOARD_ID_SUPPORT
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select BOARD_ROMSIZE_KB_4096
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select COMMON_CBFS_SPI_WRAPPER
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_SPI
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select EC_SOFTWARE_SYNC
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select RAM_CODE_SUPPORT
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select SOC_ROCKCHIP_RK3288
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select HAVE_HARD_RESET
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select MAINBOARD_DO_NATIVE_VGA_INIT
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_BOOTBLOCK_INIT
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select HAVE_HARD_RESET
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select RAM_CODE_SUPPORT
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select RETURN_FROM_VERSTAGE
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select SOC_ROCKCHIP_RK3288
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select SPI_FLASH
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select SPI_FLASH_GIGADEVICE
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select SPI_FLASH_WINBOND
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@ -45,20 +42,12 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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string
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default "Veyron_Jerry"
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default "Veyron_Brain"
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config MAINBOARD_VENDOR
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string
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default "Google"
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 0
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config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
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int
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default 100
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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@ -17,8 +17,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
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#define __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
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#ifndef __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H
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#define __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H
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#include <boardid.h>
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#include <gpio.h>
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@ -29,4 +29,4 @@
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/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */
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#endif /* __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H */
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#endif /* __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H */
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@ -45,6 +45,8 @@ void bootblock_mainboard_early_init()
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void bootblock_mainboard_init(void)
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{
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gpio_output(GPIO(7, A, 0), 1); /* Power LED */
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/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
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setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
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setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
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@ -71,9 +73,5 @@ void bootblock_mainboard_init(void)
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writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
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rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
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/* spi0 for chrome ec */
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writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
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setup_chromeos_gpios();
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}
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@ -1,4 +1,4 @@
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/*
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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@ -19,8 +19,6 @@
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#include <boot/coreboot_tables.h>
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#include <console/console.h>
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#include <ec/google/chromeec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <gpio.h>
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#include <string.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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@ -28,15 +26,12 @@
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#include "board.h"
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#define GPIO_WP GPIO(7, A, 6)
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#define GPIO_LID GPIO(0, A, 6)
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#define GPIO_POWER GPIO(0, A, 5)
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#define GPIO_RECOVERY GPIO(0, B, 1)
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#define GPIO_ECINRW GPIO(0, A, 7)
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void setup_chromeos_gpios(void)
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{
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gpio_input(GPIO_WP);
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gpio_input_pullup(GPIO_LID);
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gpio_input(GPIO_POWER);
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gpio_input_pullup(GPIO_RECOVERY);
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}
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@ -55,20 +50,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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/* Recovery: active low */
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gpios->gpios[count].port = GPIO_RECOVERY.raw;
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gpios->gpios[count].polarity = ACTIVE_HIGH;
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gpios->gpios[count].value = get_recovery_mode_switch();
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gpios->gpios[count].polarity = ACTIVE_LOW;
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gpios->gpios[count].value = gpio_get(GPIO_RECOVERY);
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strncpy((char *)gpios->gpios[count].name, "recovery",
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GPIO_MAX_NAME_LENGTH);
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count++;
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/* Lid: active high */
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gpios->gpios[count].port = GPIO_LID.raw;
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gpios->gpios[count].polarity = ACTIVE_HIGH;
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gpios->gpios[count].value = -1;
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strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
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count++;
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/* Power:GPIO active high */
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/* Power Button: GPIO active low */
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gpios->gpios[count].port = GPIO_POWER.raw;
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gpios->gpios[count].polarity = ACTIVE_LOW;
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gpios->gpios[count].value = -1;
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@ -84,14 +72,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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GPIO_MAX_NAME_LENGTH);
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count++;
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/* EC in RW: GPIO active high */
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gpios->gpios[count].port = GPIO_ECINRW.raw;
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gpios->gpios[count].polarity = ACTIVE_HIGH;
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gpios->gpios[count].value = -1;
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strncpy((char *)gpios->gpios[count].name, "EC in RW",
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GPIO_MAX_NAME_LENGTH);
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count++;
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/* Reset: GPIO active high (output) */
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gpios->gpios[count].port = GPIO_RESET.raw;
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gpios->gpios[count].polarity = ACTIVE_HIGH;
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@ -113,15 +93,7 @@ int get_developer_mode_switch(void)
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int get_recovery_mode_switch(void)
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{
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uint32_t ec_events;
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/* The GPIO is active low. */
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if (!gpio_get(GPIO_RECOVERY))
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return 1;
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ec_events = google_chromeec_get_events_b();
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return !!(ec_events &
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
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return !gpio_get(GPIO_RECOVERY);
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}
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int get_write_protect_state(void)
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@ -22,5 +22,4 @@ chip soc/rockchip/rk3288
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device cpu_cluster 0 on end
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register "vop_id" = "1"
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register "framebuffer_bits_per_pixel" = "16"
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register "lcd_power_on_udelay" = "200000"
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end
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@ -46,20 +46,6 @@ static void configure_usb(void)
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gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
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}
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static void configure_sdmmc(void)
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{
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writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
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/* use sdmmc0 io, disable JTAG function */
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writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
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/* Note: these power rail definitions are copied in romstage.c */
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rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
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rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
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gpio_input(GPIO(7, A, 5)); /* SD_DET */
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}
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static void configure_emmc(void)
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{
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writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
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@ -91,19 +77,9 @@ static void configure_vop(void)
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/* lcdc(vop) iodomain select 1.8V */
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writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
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switch (board_id()) {
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case 2:
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rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */
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rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
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rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
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break;
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default:
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gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
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rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
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gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
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rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
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break;
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}
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rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
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rk808_configure_ldo(PMIC_BUS, 7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
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rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
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}
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static void mainboard_init(device_t dev)
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@ -111,7 +87,6 @@ static void mainboard_init(device_t dev)
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gpio_output(GPIO_RESET, 0);
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configure_usb();
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configure_sdmmc();
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configure_emmc();
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configure_codec();
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configure_vop();
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@ -137,21 +112,8 @@ void lb_board(struct lb_header *header)
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dma->range_size = _dma_coherent_size;
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}
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/* called from rk3288 display.c, but there is no backlight for this platform */
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void mainboard_power_on_backlight(void)
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{
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switch (board_id()) {
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case 2:
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gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
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gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
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mdelay(10);
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gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
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break;
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default:
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gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
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mdelay(10);
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gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
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mdelay(10);
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gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
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break;
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}
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return;
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}
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