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Merge all spd_addr.h into the resp. romstage.c files. 

Except for one instance the spd_addr.h were now very tiny, there's not
much point in keeping that stuff in an extra file. The only user of those
files is the romstage.c file anyway.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-11-20 20:36:40 +00:00
parent d773fd370a
commit 26535d6e28
12 changed files with 144 additions and 283 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

94
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -39,6 +39,7 @@
#include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h> #include <lib.h>
#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c" #include "northbridge/amd/amdfam10/reset_test.c"
@ -105,7 +106,98 @@ static int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
#include "spd_addr.h" static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 8
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 12
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 16
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 20
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 24
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 32
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 48
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

115
src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h
View File

@ -1,115 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 8
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 12
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 16
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 20
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 24
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 32
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 48
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};

11
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -44,6 +44,7 @@
#include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h> #include <lib.h>
#include <spd.h>
#include "cpu/amd/model_10xxx/apic_timer.c" #include "cpu/amd/model_10xxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
@ -98,7 +99,15 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
#include "spd_addr.h" static const u8 spd_addr[] = {
// switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

32
src/mainboard/hp/dl165_g6_fam10/spd_addr.h
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
// switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};

10
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -33,6 +33,7 @@
#include <console/console.h> #include <console/console.h>
#include <usbdebug.h> #include <usbdebug.h>
#include <lib.h> #include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/model_10xxx_rev.h>
@ -116,7 +117,14 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
} }
#include "spd_addr.h" static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

31
src/mainboard/msi/ms9652_fam10/spd_addr.h
View File

@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};

10
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -33,6 +33,7 @@
#include <console/console.h> #include <console/console.h>
#include <lib.h> #include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/model_10xxx_rev.h>
@ -117,7 +118,14 @@ static void sio_setup(void)
} }
#include "spd_addr.h" static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

31
src/mainboard/supermicro/h8dmr_fam10/spd_addr.h
View File

@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};

16
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -33,6 +33,7 @@
#include <console/console.h> #include <console/console.h>
#include <lib.h> #include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/model_10xxx_rev.h>
@ -120,7 +121,20 @@ static void sio_setup(void)
} }
#include "spd_addr.h" static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
//third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
//forth node
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
#endif
};
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)

37
src/mainboard/supermicro/h8qme_fam10/spd_addr.h
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@ -1,37 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
//third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
//forth node
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
#endif
};

9
src/mainboard/tyan/s2912_fam10/romstage.c
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@ -33,6 +33,7 @@
#include <console/console.h> #include <console/console.h>
#include <usbdebug.h> #include <usbdebug.h>
#include <lib.h> #include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/model_10xxx_rev.h>
@ -120,7 +121,13 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
} }
#include "spd_addr.h" static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

31
src/mainboard/tyan/s2912_fam10/spd_addr.h
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@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};