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rockchip/rk3399: remove the delay for enabling SSC 

The hang was caused by deasserting the reset before, it had been delayed 20us
fixing the hang issue.

So we can remove this delay for now.

Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Caesar Wang 2017-05-16 08:39:40 +08:00 committed by Julius Werner
parent c7ccb6b29f
commit 2684efc492
1 changed files with 0 additions and 5 deletions
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5
src/soc/rockchip/rk3399/clock.c
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@ -356,11 +356,6 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
{ {
u32 divval; u32 divval;
/*
* TODO find the root cause why is the delay needed, otherwise sometimes
* hang somewhere with reboot tests.
*/
udelay(30);
assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6); assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6);
/* /*