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nb/intel/haswell: Use PCI bitwise ops 

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I99379299f7e744a3e906bdbc46d55060d9c75d6a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42153
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-06-07 22:19:21 +02:00 committed by Felix Held
parent aab226cc83
commit 26886076f4
2 changed files with 2 additions and 7 deletions
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6
src/northbridge/intel/haswell/early_init.c
View File

@ -37,7 +37,6 @@ static void haswell_setup_igd(void)
{
bool igd_enabled;
u16 ggc;
u8 reg8;
printk(BIOS_DEBUG, "Initializing IGD...\n");
@ -59,10 +58,7 @@ static void haswell_setup_igd(void)
}
/* Enable 256MB aperture */
reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC);
reg8 &= ~0x06;
reg8 |= 0x02;
pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8);
pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
}
static void start_peg2_link_training(const pci_devfn_t dev)

3
src/northbridge/intel/haswell/minihd.c
View File

@ -59,8 +59,7 @@ static void minihd_init(struct device *dev)
printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Mini-HD configuration */
reg32 = read32(base + 0x100c);